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Computing (ICOCO), IEEE International Conference on

作者： Sian Lun Lau Jiayi Lew Chiung Ching Ho Simon Su School of Engineering and Technology Sunway University Bandar Sunway Malaysia DoD Supercomputing Resource Center U.S. Army Research Laboratory (ARL) Aberdeen Proving Ground MD

ISBN: (纸本)9781665436908

Annotation are essential in using machine learning for object detection in images. However, good detection will require high quality annotations for supervised learning-based techniques. It is also known that manual annotation by human experts are laborious, tedious and error-prone. This problem is more so challenging in physical sciences images, such as liquid droplets or crystals. In this paper, we suggest a minimal effort approach to train YOLOv3 models using a relatively smaller set of training data for liquid droplet images. The proposed approach uses only minimal amount of annotations or annotated images, and naively build training data set using YOLOv3 models. The investigation compares two approach variants and discuss the results as an exploratory work in finding suitable semi-automatic image annotation techniques for object detection in liquid droplet images.

关键词： Liquids Annotations Training data Image annotation Object detection Manuals Machine learning

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Dynamic Collaborative Visualization Ecosystem to Support the Analysis of Large-Scale Disparate Data

Dynamic Collaborative Visualization Ecosystem to Support the...

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IEEE International Conference on Big Data

作者： Christopher Koehler Andrew Berger Raksha Rajashekar Thomas Wischgoll Simon Su Data Analytics Division Universal Technology Corporation Dayton United States Computer Science Department Wright State University Dayton United States DoD Supercomputing Resource Center US Army Research Laboratory Maryland United States

ISBN: (数字)9781728108582

ISBN: (纸本)9781728108599

There is no one display device or software package that is ideally suited for interactively visualizing related nonspatial, 1D, 2D, 3D, and 4D datasets. This is a major drawback, as the benefits of interactive visualization and advanced display technologies cannot be brought to bear. The Dynamic Collaborative Visualization Ecosystem (DynaCoVE) framework addresses this limitation by unifying SciVis, InfoVis, and display technology tools. Pre-existing packages are wrapped as DynaCoVE clients. This entails tracking user interactions with their GUI's and also automatically updating them in response to cues from the DynaCoVE server. The DynaCoVE server then acts as a message broker between many collaborating clients. A messaging protocol was defined based on ZeroMQ's majordomo protocol to enable efficient communication between clients and the server. Thus, visualization software packages that were never intended to be used together can be linked to perform cross display visual analytics. The system is intended to be data and user centric while remaining software, algorithm and display agnostic. This is accomplished in part by providing a common metavisualization graph interface to setup cross-display visualizations. To date DynaCoVE clients for Looker, VisIt, and VTK have been tested together with traditional monitors, tiled displays, and an immersive CAVE-type system.

关键词： Data visualization Tools Servers Visual analytics Ecosystems Collaboration Three-dimensional displays

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High performance computing simulations of spall phenomenon in a submicron thick nanocrystalline aluminum

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Modelling and Simulation in Materials Science and Engineering 2019年第6期27卷 065015-065015页

作者： Valisetty, R. Dongare, A. Ianni, J. Computational and Information Sciences Directorate Army Research Laboratory U.S. Army Combat Capabilities Development Command Aberdeen Proving GroundMD21005 United States Department of Materials Science and Engineering Institute of Materials Science University of Connecticut StorrsCT06269 United States Leidos ARL DoD Supercomputing Resource Center Aberdeen Proving GroundMD21005 United States

The spall failure phenomenon is investigated at nano-scale in a plate-on-plate impact configuration using large-scale molecular dynamics (MD) high performance computing (HPC) simulations4 on three multi-billion 0.5 μm thick nanocrystalline aluminum (nc-Al) systems, each with an average grain size in the range of 18-100 nm and each under impact velocities in the range of 0.7-1.5 km s-1. Using a material conserving atom section-averaging process, distributions of several mechanical responses were obtained and the extremely transient spall failure phenomena were located in the interaction zones of the stress release waves released from the impacted and free ends of the atom systems. The spall zones' thicknesses were estimated along with the spall strengths. For the nc-Al atom systems, the spall strength was observed to increase as the impact velocity increased from 0.7 to 1.5 km s-1, but only showed a slight decrease as the grain size increased from 18 to 100 nm. The spall strengths thus estimated from the stress release waves' interaction zones were found to be conservative when compared to the traditional estimates obtained from the pullback velocity signatures in the free-end velocity evolutions. The MD results were further analyzed using a crystal analysis algorithm and a twin dislocation identification method to obtain the densities of the atomistic microstructures evolving under the interaction of the stress release waves. High-fidelity large-scale HPC simulation results showed that certain dislocation partials strongly influenced the spall response. The Stair-rod type dislocation partials increased by more than a factor of 10 during the interaction of the stress release waves as the spall failure commenced. © 2019 IOP Publishing Ltd.

关键词： Velocity

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Parametric domain representation of multi-block structured meshes for strong-shock flow simulations

Parametric domain representation of multi-block structured m...

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AIAA Aerospace Sciences Meeting, 2018

作者： Gosse, Ryan Mackintosh, Cameron Vogiatzis, Konstantinos Williams, Charles AFRL/RQHF U.S. Air Force Research Laboratory Wright-Patterson Air Force Base 2210 Eighth Street OH45433 United States DoD HPCMP PETTT/Engility Corp. DoD Supercomputing Resource Center AFRL/RCM U.S. Air Force Research Laboratory Wright-Patterson Air Force Base 2435 Fifth Street OH45433 United States

ISBN: (数字)9781624105241

ISBN: (纸本)9781624105241

Procedures to parametrically represent two- and three-dimensional domains, used in generation of structured meshes for CFD (Computational Fluid Dynamics) simulations, with Bezier surfaces and volumes have been developed. They provide compact data structures, exhibiting several orders of magnitude reduction in size for the same fidelity that can facilitate scalable mesh generation, decomposition and data analysis and eliminate bandwidth saturation. A demonstration of multi-block mesh generation using an example shape pertinent to compressible strong-shock flow simulations is presented. © 2018, American Institute of Aeronautics and Astronautics Inc, AIAA. All rights reserved.

关键词： Mesh generation

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A QM/MM equation-of-motion coupled-cluster approach for predicting semiconductor color-center structure and emission frequencies

arXiv

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arXiv 2017年

作者： Lutz, Jesse J. Duan, Xiaofeng F. Burggraf, Larry W. ORISE fellow residing at Department of Engineering Physics Air Force Institute of Technology Wright-Patterson Air Force Base OH45433 United States Air Force Research Laboratory DoD Supercomputing Resource Center Wright-Patterson Air Force Base OH45433 United States Air Force Institute of Technology Wright-Patterson Air Force Base OH45433 United States

Valence excitation spectra were computed for deep-center silicon-vacancy defects in 3C, 4H, and 6H silicon carbide (SiC) and comparisons were made with literature photoluminescence measurements. Optimizations of nuclear geometries surrounding the defect centers were performed within a Gaussian basis-set framework using many-body perturbation theory or density functional theory (DFT) methods, with computational expenses minimized by a QM/MM technique called SIMOMM. Vertical excitation energies were subsequently obtained by applying excitation-energy, electronattached, and ionized equation-of-motion coupled-cluster (EOMCC) methods, where appropriate, as well as time-dependent (TD) DFT, to small models including only a few atoms adjacent to the defect center. We consider the relative quality of various EOMCC and TD-DFT methods for (i) energy-ordering potential ground states differing incrementally in charge and multiplicity, (ii) accurately reproducing experimentally measured photoluminescence peaks, and (iii) energy-ordering defects of different types occurring within a given polytype. The extensibility of this approach to transition-metal defects is also tested by applying it to silicon-substituted chromium defects in SiC and comparing with measurements. It is demonstrated that, when used in conjunction with SIMOMM-optimized geometries, EOMCC-based methods can provide a reliable prediction of the ground-state charge and multiplicity, while also giving a quantitative description of the photoluminescence spectra, accurate to within 0.1 eV of measurement for all cases considered. Copyright © 2017, The Authors. All rights reserved.

关键词： Ground state

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High-Performance Computing Interfaces for High-Fidelity Radar Modeling

High-Performance Computing Interfaces for High-Fidelity Rada...

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dod High Performance Computing Modernization Program Users Group

作者： Donald J. Fabozzi II Carl M. Holmberg Bruce Duncan Robert Hancock Jeff McKay Maui High Performance Computing Center DoD Supercomputing Resource Center (MHPCC DSRC) Kihei HI CAESoft Corporation Rockwall TX

This paper describes the interfaces to a high performance computing (HPC)-based high-fidelity radar simulation including task partitioning, parametric control, and visualization. This capability approximates realistic airborne surveillance radar platforms, and performs near-real-time flight test simulations through the integration of a Department of Defense (dod)-developed radar simulation application, and the Maui High Performance Computing center, dod supercomputing resource center's (MHPCC DSRC) 9,216 core "Mana" HPC.

关键词： Transmitters Computational modeling Radar Atmospheric modeling High performance computing Directive antennas Decision support systems

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Accelerating a Sparse Matrix Iterative Solver Using a High Performance Reconfigurable Computer

Accelerating a Sparse Matrix Iterative Solver Using a High P...

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dod High Performance Computing Modernization Program Users Group

作者： Gerald R. Morris Ricky Y. McGruder Khalid H. Abed US Army Engineer Research & Development Center DoD Supercomputing Resource Center (ERDC DSRC) Vicksburg MS Department of Computer Engineering Jackson State University Jackson MS

High performance reconfigurable computers (HPRCs), which combine general-purpose processors (GPPs) and field programmable gate arrays (FPGAs), are now commercially available. These interesting architectures allow for the creation of reconfigurable processors. HPRCs have already been used to accelerate integer and fixed-point applications. However, extensive parallelism and deeply pipelined floating-point cores are necessary to make MHz-scale FPGAs competitive with GHz-scale GPPs, thus making it difficult to accelerate certain kinds of floating-point kernels. Kernels with variable length nested loops, e.g., sparse matrix-vector multiply, have been problematic because of the loop-carried dependence associated with the pipelined floating-point units. While hardware description language (HDL)-based kernels have shown moderate success in addressing this problem, the use of a high-level language (HLL)-based approach to accelerate such applications has been rather elusive. If HPRCs are to become a part of mainstream military and scientific computing, we should emphasize the use of HLL-based programming, whenever possible, rather than HDL-based hardware design. The primary reason is the increased programmer productivity associated with HLLs when compared with HDLs. For example, the floating-point addition statement z = x+y, a single line in an HLL, corresponds to hundreds of lines of HDL. In this paper, we describe the design and implementation of a sparse matrix Jacobi processor to solve systems of linear equations, Ax=b. The parallelized, deeply pipelined, IEEE-754-compliant 32-bit floating-point sparse matrix Jacobi iterative solver runs on a contemporary HPRC. The FPGA-based components are implemented using only an HLL (the C programming language) and the Carte HLL-to-HDL compiler. An HLL-based streaming accumulator allows for the implementation of fully pipelined loops and results in a 2.5-fold wall clock runtime speedup when compared with an equivalent software-only i

关键词： Jacobian matrices Sparse matrices Program processors Field programmable gate arrays Kernel Hardware Computers

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Mapping Hierarchical Multiple File VHDL Kernels onto an SRC-7 High Performance Reconfigurable Computer

Mapping Hierarchical Multiple File VHDL Kernels onto an SRC-...

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dod High Performance Computing Modernization Program Users Group

作者： Gerald R. Morris Khalid H. Abed US Army Engineer Research & Development Center DoD Supercomputing Resource Center (ERDC DSRC) Vicksburg MS Department of Computer Engineering Jackson State University Jackson MS

The increasing computational requirements of today's software systems have led researchers to investigate ways of accelerating military and scientific computing applications. Contemporary field programmable gate arrays (FPGAs) are now equipped with multimillion gate logic fabrics, faster clock rates, reasonably large on-chip memory, and fast I/O resources for off-chip communication. The use of FPGAs as reconfigurable computational units complementing a fixed computational device such as a general-purpose processor (GPP) is the basic idea behind what are known as high performance reconfigurable computers (HPRCs). These exciting architectures allow development of reconfigurable processors that target the computationally intensive parts of a given application. Ideally, one should use a high-level language (HLL) rather than a hardware description language (HDL) to implement HPRC-based applications. However, in order to accelerate some applications, an HDL must be used to design computational kernels. The HPRC used in the joint research project between the U.S. Army Engineer Research and Development center {dod supercomputing} resource center (ERDC DSRC) and Jackson State University (JSU) employs the SRC Computers' Carte development environment. Carte allows application development using a conventional HLL, an HLL-to-HDL compiler, and custom-built VHDL-based kernels ("user macros" in SRC parlance). Currently, the off-the-shelf Carte mechanism for incorporating user macros does not directly support the common case of a multiple file VHDL hierarchy. This research explores a novel approach that allows multiple file VHDL kernels to be mapped onto the SRC-7 HPRC. The approach facilitates the development of FPGA-based elements via a hybrid technique that uses the Carte HLL-to-HDL compiler in conjunction with multiple file VHDL-based user macros. This paper describes the use of this novel approach to map a parameterized, parallelized, and pipelined FPGA-based sparse matrix vect

关键词： Sparse matrices Hardware Field programmable gate arrays Kernel Hardware design languages Computers

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Finding the Best HPCMP Architectures Using Benchmark Application Results for TI-09

Finding the Best HPCMP Architectures Using Benchmark Applica...

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dod High Performance Computing Modernization Program Users Group

作者： Laura Brown Paul M. Bennett Mark Cowan Carrie Leach Thomas C. Oppe DoD Supercomputing Resource Center ERDC DSRC Information Technology Laboratory U.S. Army Engineer Research and Development Center Vicksburg MS USA

Time-to-solution and scalability of an application can vary greatly from one computer architecture to another. It is important then to consider the appropriateness of architectures with respect to applications to make the most efficient use of available resources. However, the number of applications currently used on systems within the High Performance Computing Modernization Program (HPCMP) is very large. This paper, therefore, focuses solely on codes within the HPCMP Technology Insertion 2009 (TI-09) Applications Benchmarking Suite. These codes include Adaptive Mesh Refinement (AMR), Air Vehicles Unstructured Solver (AVUS), CTH, General Atomic and Molecular Electronic Structure System (GAMESS), HYbrid Coordinate Ocean Model (HYCOM), Improved Concurrent Electromagnetic Particle In Cell (ICEPIC), and Large-scale Atomic/Molecular Massively Parallel Simulator (LAMMPS). This paper evaluates the parallel performance-per-processor of each of these seven codes on major systems within the Program. This, in turn, can guide users and developers in selecting appropriate architectures for each code.

关键词： Computer architecture Dynamic range Adaptation model Mathematical model Laboratories Benchmark testing Atmospheric modeling

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Improving Performance of Codes with Large/Irregular Stride Memory Access Patterns via High Performance Reconfigurable Computers

Improving Performance of Codes with Large/Irregular Stride M...

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dod High Performance Computing Modernization Program Users Group

作者： Khalid H. Abed Gerald R. Morris Department of Computer Engineering School of Engineering Jackson MS USA DoD Supercomputing Resource Center ERDC DSRC U.S. Army Engineer Research and Development Center Vicksburg MS USA

Parallel codes with large-stride/irregular-stride (L/I) memory access patterns, e.g., sparse matrix and linked list codes, often perform poorly on mainstream clusters because of the general purpose processor (GPP) memory hierarchy. High performance reconfigurable computers (HPRCs) are parallel computing clusters containing multiple GPPs and field programmable gate arrays (FPGAs) connected via a high-speed network. In this research, simple 64-bit floating-point parallel codes are used to illustrate the performance impact of L/I memory accesses in software (SW) and FPGA-augmented (FA) codes and to assess the benefits of mapping L/I-type codes onto HPRCs. The experiments reveal that large-stride SW codes, particularly those involving data reuse, experience severe performance degradation compared with unit-stride SW codes. In contrast, large-stride FA codes experience minimal degradation compared with unit-stride FA codes. More importantly, for codes that involve data reuse, the experiments demonstrate performance improvements of up to nearly tenfold for large-stride FA codes compared with large-stride SW codes.

关键词： Field programmable gate arrays Computers Sparse matrices Kernel Parallel processing Equations

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