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Compact Model Build Upon Dynamic Weighting Artificial Neural Network Approach for Complementary Field Effect Transistors

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IEEE Transactions on Electron Devices 2024年第1期71卷 246-253页

作者： Butola, Rajat Li, Yiming Kola, Sekhar Reddy National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Electrical Engineering and Computer Science International Graduate Program Hsinchu300093 Taiwan Institute of Pioneer Semiconductor Innovation The Institute of Artificial Intelligence Innovation National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Electrical Engineering and Computer Science International Graduate Program The Institute of Communications Engineering the Institute of Biomedical Engineering Department of Electronics and Electrical Engineering Hsinchu300093 Taiwan

In this work, a dynamic weighting-artificial neural network (DW-ANN) methodology is presented for quick and automated compact model (CM) generation. It takes advantage of both TCAD simulations for high accuracy and SPICE simulations for cost-effectiveness. This methodology is developed for gate-all-around (GAA) silicon (Si) nanosheet (NS) complementary field effect transistor (CFET), a potential candidate for future CMOS technology due to its innate properties. The critical process variation (PV) sources that severely degrade the CFET performance are estimated using DW-ANN. It reduces the computation cost and predicts the effects of PV sources with less than 1% error. Furthermore, a compact DW-ANN-based Verilog-A model has been developed that captures the dc as well as transient behavior accurately for circuit-level analysis. CFET-based circuits such as inverter, 6T-static random access memory (SRAM), and ring oscillator (RO) are characterized and implemented using DW-ANN-based CM. The overall average error of the model is reported as less than 2%. Therefore, the proposed device and circuit modeling approach provides a feasible solution for the rapid compact modeling of new emerging devices with good convergence and high accuracy. © 1963-2012 IEEE.

关键词： Neural networks

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A Physical-Based Artificial Neural Networks Compact Modeling Framework for Emerging FETs

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IEEE Transactions on Electron Devices 2024年第1期71卷 223-230页

作者： Yang, Ya-Shu Li, Yiming Kola, Sekhar Reddy Reddy National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory The Institute of Communications Engineering Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Institute of Communications Engineering Institute of Biomedical Engineering Department of Electronics and Electrical Engineering Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Electrical Engineering and Computer Science International Graduate Program Hsinchu300093 Taiwan

We report a compact modeling framework based on the Grove-Frohman (GF) model and artificial neural networks (ANNs) for emerging gate-all-around (GAA) MOSFETs. The framework consists of two ANNs;the first ANN constructed with the drain current model not only can capture the main trend of device I - V characteristics but also can predict its variation even when the amount of training data for the ANN is insufficient or outside the range of applied biases. The second one is then designed to improve the model accuracy by further minimizing the errors between the target and the model outputs. We implement the proposed framework to accurately model emerging GAA nanosheet (NS) MOSFETs and complementary FETs (CFETs) without suffering from divergent issues in circuit simulation. In addition, nonphysical behaviors, such as nonzero current at zero bias, do not occur in the modeling framework. Compared to recently reported machine-learning (ML) models, our approach can achieve a similar level of model accuracy with merely 20% amount of the training data. © 1963-2012 IEEE.

关键词： Neural networks

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Statistical Device Simulation and Machine Learning of Process Variation Effects of Vertically Stacked Gate-All-Around Si Nanosheet CFETs

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IEEE Transactions on Nanotechnology 2024年 23卷 386-392页

作者： Kola, Sekhar Reddy Li, Yiming Butola, Rajat National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Electrical Engineering and Computer Science International Graduate Program Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Department of Electronics and Electrical Engineering Institute of Communications Engineering Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Institute of Biomedical Engineering Institute of Pioneer Semiconductor Innovation Institute of Artificial Intelligence Innovation Hsinchu300093 Taiwan

In this study, we report the process variation effect (PVE) including the work function fluctuation (WKF) on the DC/AC characteristic fluctuation of stacked gate-all-around silicon complementary field-effect transistors (CFETs). The PVE affects characteristic fluctuation significantly;in particular, for the variability of off-state current. Owing to the bottom channel of a fin-type, the P-FET suffers from the worst off-state current fluctuation (more than 200% variation) compared to the N-FET. The device variability induced by the WKF is marginal because of amorphous-type metal grains. As input features to an artificial neural network (ANN) model, low and high work function values, as well as parameters of PVE that have prevalent effects on CEFT transfer characteristics are further considered and modeled. The estimated values of R2-score prove that the ANN model properly grasps information from the dataset successfully;thus, it can be used to model emerging CFETs for circuit simulation. © 2002-2012 IEEE.

关键词： Neural networks

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Electrical Characteristic and Power Fluctuations of GAA Si NS CFETs by Simultaneously Considering Six Process Variation Factors

IEEE Open Journal of Nanotechnology

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IEEE Open Journal of Nanotechnology 2023年 4卷 229-238页

作者： Kola, Sekhar Reddy Li, Yiming National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Electrical Engineering and Computer Science International Graduate Program Hsinchu300093 Taiwan Parallel and Scientific Computing Laboratory National Yang Ming Chiao Tung University Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Institute of Communications Engineering Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Institute of Biomedical Engineering Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Department of Electronics and Electrical Engineering Hsinchu300093 Taiwan

Characteristic variability induced by process variation effect (PVE) is one of technological challenges in semiconductor industry. In this work, we computationally study electrical characteristic and power fluctuations induced by six factors of PVE of the gate-all-around (GAA) silicon (Si) nanosheet (NS) complementary field-effect-transistors (CFETs) which are formed by vertically stacking n-FET on top of p-FET. Among the six factors, NS thickness (TNS), NS width (WNS), and gate length (LG) are identified as crucial factors contributing to large variations in device characteristics. The p-FET exhibits substantial off-state current fluctuation (about 151%) due to the bottom parasitic channel leakages. Compared with the magnitudes of dynamic and short circuit powers, the static power is marginal, but it possesses the largest fluctuation (up to 148%). If we assume that each factor of PVE has the same probability distribution as the others and all are mutually independent, the statistical sum of their power fluctuations will exhibit more than 50% overestimations, compared with the results when all factors are considered simultaneously. © 2020 IEEE.

关键词： III-V semiconductors

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DC/AC/RF Characteristics of Multi-Channel GAA NS FETs with ML and BL MoS2

DC/AC/RF Characteristics of Multi-Channel GAA NS FETs with M...

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international Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

作者： Yueh-Ju Chan Sekhar Reddy Kola Yiming Li Institute of Communications Engineering and Parallel and Scientific Computing Laboratory National Yang Ming Chiao Tung Univeristy Hsinchu Taiwan EECS International Graduate Program and Parallel and Scientific Computing Laboratory National Yang Ming Chiao Tung Univeristy Hsinchu Taiwan

For the first time, we examine the performance of gate-all-around nanosheet field effect transistor (GAA NS FET) with both monolayer (ML) and bilayer (BL) molybdenum disulfide (MoS 2 ). As compared to the control sample of silicon (Si), MoS 2 devices exhibit reduced short-channel effects (SCE) owing to its larger band gap and larger effective mass. The GAA NS FET with BL MoS 2 possesses moderate energy bandgap and large channel thickness which exhibits superior on state current and voltage gain.

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Enhancing the Performance of E-Mode AlGaN/GaN HEMTs With Recessed Gates Through Low-Damage Neutral Beam Etching and Post-Metallization Annealing

IEEE Open Journal of Nanotechnology

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IEEE Open Journal of Nanotechnology 2023年 4卷 150-155页

作者： Chen, Yi-Ho Ohori, Daisuke Aslam, Muhammad Lee, Yao-Jen Li, Yiming Samukawa, Seiji National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Graduate Degree Program of College of Electrical and Computer Engineering Hsinchu300093 Taiwan Tohoku University Institute of Fluid Science Sendai980-8577 Japan National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Electrical Engineering and Computer Science International Graduate Program Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Institute of Pioneer Semiconductor Innovation Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Institute of Communications Engineering Institute of Biomedical Engineering Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Department of Electronics and Electrical Engineering Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Institute of Communications Engineering Hsinchu300093 Taiwan

This study investigated the electrical properties of AlGaN/GaN high-electron-mobility transistors (HEMTs) with varied recess depths under the gate electrode. We demonstrated a recess depth of approximately 6 nm, which was achieved through neutral beam etching (NBE) technique with a low etch rate of 1.8 nm/min, resulting in device enhancement-mode (E-mode) behavior with threshold voltage (Vth) of 0.49 V. The effects of post-metallization annealing (PMA) on the device performance were also examined. The results revealed that PMA treatment improves the DC characteristics of the devices, including maximum drain current (IDMAX), transconductance (gm), subthreshold swing (SS), on-off ratio, and off-state leakage current, with maximum enhancement percentage of 18.3% for IDMAX, 3758% for on-off ratio, and 54.3% for SS. Moreover, this study compared the recess depths of metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) with the SiN dielectric layer. The results showed that MIS-HEMTs exhibit more negative Vth values, which can be attributed to the controlled surface states achieved through passivation. © 2020 IEEE.

关键词： Etching

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A Comprehensive Technique Based on Machine Learning for Device and Circuit Modeling of Gate-All-Around Nanosheet Transistors

IEEE Open Journal of Nanotechnology

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IEEE Open Journal of Nanotechnology 2023年 4卷 181-194页

作者： Butola, Rajat Li, Yiming Kola, Sekhar Reddy National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Electrical Engineering and Computer Science International Graduate Program Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Institute of Communications Engineering the Institute of Biomedical Engineering the Department of Electronics and Electrical Engineering the Institute of Pioneer Semiconductor Innovation and the Institute of Artificial Intelligence Innovation Hsinchu300093 Taiwan

Machine learning (ML) is poised to play an important part in advancing the predicting capability in semiconductor device compact modeling domain. One major advantage of ML-based compact modeling is its ability to capture complex relationships and patterns in large datasets. Therefore, in this paper a novel design scheme based on dynamically adaptive neural network (DANN) is proposed to develop fast and accurate compact model (CM). This framework constitutes a powerful yet computationally efficient methodology and exhibits emergent dynamic behaviors. This paper demonstrates that the compact model based on ML can be designed to replicate the performance of conventional compact model for nanodevices. For this work, gate-all-around (GAA) nanosheet (NS) device characteristics are comprehensively analyzed for process variability sources using the proposed model. The device geometry parameters such as channel length, nanosheet width and nanosheet thickness are fed as input features to the DANN model. The adaptive neural network learns dynamically by updating weights of the model in accordance with the input features and achieves accurate neural weight convergence. The proposed model predicted the electrical characteristics of NS devices with less than 1% error rate. The model is also implemented and validated for the simulations of digital circuit designs such as inverter, and logic gates. ©;2023 The Authors.

关键词： Circuit simulation

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Mechanism of Threshold Voltage Instability in Double Gate α-IGZO Nanosheet TFT under Bias and Temperature Stress

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IEEE Journal of the Electron Devices Society 2024年 12卷 464-471页

作者： Aslam, Muhammad Chang, Shu-Wei Chen, Yi-Ho Lee, Yao-Jen Li, Yiming Lee, Wen-Hsi Parallel and Scientific Computing Laboratory National Yang Ming Chiao Tung University Hsinchu300093 Taiwan Electrical Engineering and Computer Science International Graduate Program National Yang Ming Chiao Tung University Hsinchu300093 Taiwan Department of Electrical Engineering National Cheng Kung University Tainan City701401 Taiwan Institute of Pioneer Semiconductor Innovation Industry Academic Innovation School National Yang Ming Chiao Tung University Hsinchu300093 Taiwan Department of Electronics and Electrical Engineering National Yang Ming Chiao Tung University Hsinchu300093 Taiwan Institute of Communications Engineering National Yang Ming Chiao Tung University Hsinchu300093 Taiwan

Amorphous indium gallium zinc oxide (a-IGZO)-based thin film transistors (TFTs) are increasingly becoming popular because of their potential in futuristic applications, including CMOS technology. Given the demand for CMOS-compatible, ultra-scaled, reliable, and high-performing devices, we fabricate and analyze scaled-channel a-IGZO-TFTs with an optimal double-gate structure, a thin nanosheet-based channel, and an effective high- κ dielectric namely HfO2. The reliably reported double gate IGZO nanosheet TFTs (DG-IGZO-NS-TFTs) are tested under positive and negative bias stress at variant temperatures, and the resulting modulations are analyzed critically. The reported DG-IGZO-NSTFTs exhibit a negative side threshold voltage shift (Δ Vth) accompanied by an increase in Ion/Ion(0) under negative bias temperature stress (NBTS) at elevated temperatures, which indicates the presence of additional charges. An anomalous negative side shifting of the Vth is observed under positive bias temperature stress (PBTS), where diffused hydrogen atoms are identified as introducing excess n-type carriers into the channel and causing the observed Δ Vth. The spectroscopic analysis is performed to establish evidence for the assumed mechanisms, and the role of individual gates is investigated in the context of performance variance under temperature-bias stress. Moreover, the partial reversibility of the stress-induced degradation is experimentally established and methodically discussed. Overall, the reported results offer a comprehensive understanding of scaled-channel DG-NS-IGZO-TFTs, which help shape performance-enhancement strategies, control degradation mechanisms, and define appropriate application scenarios. © 2013 IEEE.

关键词： Thin film transistors

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Temperature-Dependent Hydrogen Modulations of Ultra-Scaled a-IGZO Thin Film Transistor Under Gate Bias Stress

IEEE Open Journal of Nanotechnology

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IEEE Open Journal of Nanotechnology 2024年 5卷 9-16页

作者： Aslam, Muhammad Chang, Shu-Wei Chuang, Min-Hui Chen, Yi-Ho Lee, Yao-Jen Li, Yiming Parallel and Scientific Computing Laboratory National Yang Ming Chiao Tung University Hsinchu300093 Taiwan Electrical Engineering and Computer Science International Graduate Program National Yang Ming Chiao Tung University Hsinchu300093 Taiwan Department of Electrical Engineering National Cheng Kung University Tainan701401 Taiwan Institute of Communications Engineering National Yang Ming Chiao Tung University Hsinchu300093 Taiwan Graduate Degree Program of College of Electrical and Computer Engineering National Yang Ming Chiao Tung University Hsinchu300093 Taiwan Institute of Pioneer Semiconductor Innovation National Yang Ming Chiao Tung University Hsinchu300093 Taiwan Institute of Biomedical Engineering National Yang Ming Chiao Tung University Hsinchu300093 Taiwan Department of Electronics and Electrical Engineering National Yang Ming Chiao Tung University Hsinchu300093 Taiwan

Recently, a-IGZO has advanced toward the next-generation electronics system because of its compatibility with complementary metal oxide semiconductor (CMOS) and back-end-of-line (BOEL) based systems. A systematic electrical characterization of a-IGZO TFT related to reliability issues, such as positive bias temperature stress (PBTS) and negative bias temperature stress (NBTS), would entitle its integration into novel electronics systems. Unexpectedly, PBTS is characterized by the transition of positive Vth shift to negative Vth shift (ΔVth, the positive shift followed by the stress and temperature activated negative shift). This transition is attributed to charge trapping/trap-site generations and hydrogen migration to the active layer. The ΔVth shift mechanism depends on the temperature and voltage stress. On the other hand, a negative ΔVth shift has been observed during the NBTS operation and could be attributed to the hole trapping at the interface of GI/IGZO. An effective suppression of the gate leakage current has also been observed during reliability tests. Simulation results reveal a pronounced potential at the edges of source and drain regions, and considered the origin of hydrogen migration into the IGZO layer. Thermal image results also reveal the strong temperature/potential distribution at the edges of the source/drain regions, indorsing the simulation results. © 2020 IEEE.

关键词： Oxide semiconductors

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Scaling Limitations of Line TFETs at Sub-8-nm Technology Node

Scaling Limitations of Line TFETs at Sub-8-nm Technology Nod...

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2020 international Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

作者： Thoti, Narasimhulu Li, Yiming Kola, Sekhar Reddy Parallel and Scientific Computing Laboratory Eecs International Graduate Program Institute of Communications Engineering Department of Electrical and Computer Engineering Center for MmWave Smart Radar System and Technologies National Chiao Tung University 1001 Ta-Hsueh Rd Hsinchu300 Taiwan

ISBN: (纸本)9781728142326

The scope of the work is to investigate limitations in device scaling by identifying various parameters of short channel effects (SCEs) in current challenging geometries of the line tunnel field effect transistors (TFETs). Key factors of the considered device, such as the doping and the thickness (tn) of n-epitaxial region, and source-to-drain length (LSDeff) scaling cannot be tuned anymore to boost the device characteristics for the sub-8-nm technology node. The main results of this study indicates that the engineering acceptable performance are achieved at a low doping of 5 1018 cm-3, an optimal tn as low (about 0.5 nm), and a LSDeff greater than 12.5 nm. Hence, the line TFETs below sub-8-nm faces serious bottleneck of scaling and cannot be further scaled with the conventional scaling rule at all. © 2020 IEEE.

关键词： Tunnel field effect transistors

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