We report the effects of the spacer and the single-charge trap (SCT) on the voltage transfer characteristics of cylindrical-shape gate-all-around (GAA) silicon (Si) nanowire (NW) metal-oxide-semiconductor field effect...
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ISBN:
(数字)9781728182643
ISBN:
(纸本)9781728182650
We report the effects of the spacer and the single-charge trap (SCT) on the voltage transfer characteristics of cylindrical-shape gate-all-around (GAA) silicon (Si) nanowire (NW) metal-oxide-semiconductor field effect transistor (MOSFETs). We explore the impact of low-x spacer, high-x spacer, and dual spacer (DS) on electrical characteristics of the GAA Si NW MOSFET with a gate length of 10 nm. Compared with the nominal device (i.e., the device without spacer), the device with DS possesses 68.8% reduction on the normalized off-current and 29.4% increase on the normalized on-current for n- and p-type devices. Similarly, 21.1% and 3.38% improvements on the normalized high and low noise margins can be achieved for the GAA Si NW complementary metal-oxide-semiconductor (CMOS) circuit. Notably, the voltage transfer characteristics induced by the acceptor- and donor-type SCT for the CMOS circuit with DS possesses 2.64% and 3.82% enhancements for the normalized high and low noise margins compared with the nominal one.
Three-dimensional (3D) bulk fin-typed field effect transistors (FinFETs) have emerged as key devices that can scale down the technology node beyond 22-nm. However, the scaled devices have created new sources of fluctu...
Three-dimensional (3D) bulk fin-typed field effect transistors (FinFETs) have emerged as key devices that can scale down the technology node beyond 22-nm. However, the scaled devices have created new sources of fluctuation inherent in 3D geometry. The interface trap is one such fluctuation that is caused by the trapping and de-trapping of charge carriers and has an adverse effect on device characteristics and variability. In this work, we study impacts of random interface traps (RITs) on electrical characteristic of bulk FinFETs by using a 3D quantum-mechanically corrected device simulation. RIT position effects on short channel effects (SCEs) are examined with physical governed influence to show the major fluctuations. More than 50% reductions of the RITs-induced characteristic fluctuation of the germanium (Ge) devices are observed, compared with Si devices. The Ge ones can reduce SCE variations and exhibit high immunity to RITs.
In this work, our study comprises of design and investigation on negative capacitance (NC), metal-oxide-semiconductor (MOS) field effects transistors (MOSFETs) with spacer and source/drain (S/D) overlap engineering. T...
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We report for the first time a novel structure of tunneling field-effect transistors (TFETs) with ferroelectric and nanowire concepts. The device is modeled carefully to utilize the benefits of ferroelectrics through ...
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We report for the first time a novel structure of tunneling field-effect transistors (TFETs) with ferroelectric and nanowire concepts. The device is modeled carefully to utilize the benefits of ferroelectrics through metal-ferroelectric by enhancing the internal voltage across the ferroelectric region. The physical behavior of proposed design is analyzed for the improvement of device performance in comparison to the nominal ferroelectric-insulator TFET structure. The proposed design is capable in delivering impressive figures in Ion as 212 μA/μm. reasonable Ioff together with steep subthreshold swing of 33.3 mV/dec.
We for the first time study characteristic fluctuation of gate-all-around silicon nanosheet MOSFETs induced by random dopants fluctuation (RDF), interface trap fluctuation (ITF), and work function fluctuation (WKF), a...
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The purpose of this letter is to study the design and explore vertically stacked complementary tunneling field-effect transistors (CTFETs) using CFET technology for emerging technology nodes. As a prior work, the CTFE...
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We for the first time investigate the possibility to replace the device simulation for tunnel field-effect transistors (TFETs) with a machine learning (ML) algorithm. By incorporating the experimentally validated devi...
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We for the first time investigate the possibility to replace the device simulation for tunnel field-effect transistors (TFETs) with a machine learning (ML) algorithm. By incorporating the experimentally validated device simulation, a keyML technique named random forest regression (RFR) model is advanced and applied to predict characteristics of TFETs. The results of this work may benefit the design and fabrication of TFETs based on the well-trained RFR model. Very fast and accurate drain current (ID) prediction in terms of the engineering acceptable root-mean-square (RMSE) error inaugurates TFET technology with ML with a potential application to significantly reduce the computational cost.
In recent years, the GAA NS Si MOSFET has been explored as a leading technology. However, the intrinsic parameters of GAA NS Si MOSFETs are affected to varying degrees by various fluctuation sources, Statistically ind...
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In recent years, the GAA NS Si MOSFET has been explored as a leading technology. However, the intrinsic parameters of GAA NS Si MOSFETs are affected to varying degrees by various fluctuation sources, Statistically independent and identically distributed $(iid)$ assumptions on the aforementioned random variables overestimate the variability of high-frequency characteristics, compared with considering all fluctuation factors simultaneously. Notably, the random nanosized metal grains dominates the variations of voltage gain, cut-off frequency, and 3dB frequency because the random work functions strongly alter the channel surface potential.
We study the variability of vertically stacked gate-all-around silicon nanosheet (GAA Si NS) complementary field-effect transistors (CFETs). The process variation effect (PVE), the work function fluctuation (WKF), and...
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We study the variability of vertically stacked gate-all-around silicon nanosheet (GAA Si NS) complementary field-effect transistors (CFETs). The process variation effect (PVE), the work function fluctuation (WKF), and the random dopant fluctuation (RDF) of CFETs are statistically estimated using an experimentally validated device simulation technique. Among five factors of PVE, the channel thickness (T Nch /T Pch ), the channel width (W ch ), and the gate length (L G ) are significant. Owing to superior GAA channel control and increased effective gate area, both WKF and RDF are suppressed. Notably, the PVE on both N-/P-FETs of GAA Si CFET induce the largest off-state current fluctuations of 80% and 278%, respectively, because the device characteristic is very sensitive to the layer thickness and width of channel.
In this paper, for the first time, deep learning (DL) based artificial neural network (ANN) is applied to model the effects of various random variations: work function fluctuation, random dopant fluctuation, and inter...
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