In this work, we propose a deep artificial neural network (D-ANN) to estimate the work function fluctuation (WKF) on 4-channel stacked gate-all-around (GAA) silicon (Si) nanosheet (NS) and nanofin (NF) MOSFET devices ...
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In this work, we propose a deep artificial neural network (D-ANN) to estimate the work function fluctuation (WKF) on 4-channel stacked gate-all-around (GAA) silicon (Si) nanosheet (NS) and nanofin (NF) MOSFET devices for the first time. The 2-layered simple deep model can well predict the transfer characteristics for both NS/NF FET with a large number of (128) input features, utilizing considerably lesser (1100 samples) data uniformly. The resultant model is evaluated by the $\mathrm{R}^{2}$ score and RMSE to witness its competency and the average error is $< 4\%$ . We do also discuss the circuit simulation possibility by applying the ANN approach.
In this work, our study comprises of design and investigation on negative capacitance (NC), metal-oxide-semiconductor (MOS) field effects transistors (MOSFETs) with spacer and source/drain (S/D) overlap engineering. T...
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ISBN:
(数字)9781728142326
ISBN:
(纸本)9781728142333
In this work, our study comprises of design and investigation on negative capacitance (NC), metal-oxide-semiconductor (MOS) field effects transistors (MOSFETs) with spacer and source/drain (S/D) overlap engineering. The scope of the work is to boost the performance and high-energy efficiency of the studied NC-MOSFETs by using the ferro electric material (FE). The NC-MOSFETs with the spacer technology can achieve the admirable I on /I off ratio and subthreshold swing (SS), compared with planar MOSFETs. It makes device scaling possible by eliminating the short channel effect (SCE). We further estimated the effect of FE thickness and spacer, which are another critical parameter of obtaining better electrical characteristics and reducing SS.
Deep learning (DL) has significantly advanced various industries, including semiconductors, by providing sophisticated methods for analyzing emerging device data. Transfer learning (TL), a prominent DL topology, lever...
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Nanosheet line tunnel-field effect transistors (NLTFETs) are for the first time proposed by utilizing the advantages of ferroelectricity through HZO materials. Three ferroelectric line TFETs have been proposed and inv...
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ISBN:
(数字)9784863487635
ISBN:
(纸本)9781728173542
Nanosheet line tunnel-field effect transistors (NLTFETs) are for the first time proposed by utilizing the advantages of ferroelectricity through HZO materials. Three ferroelectric line TFETs have been proposed and investigated. Among these, the metal-ferroelectric-semiconductor (MFS) structure has shown superior performance than the other two variants. The factors of electric field and electron barrier tunneling have been addressed to govern the performance of these structures. In addition, the effects of the ferroelectric (Hf 0.5 Zr 0.5 O 2 ) thickness (t FE ) and the dielectric constant have been discussed. The MFS NLTFETs can effectively utilize the advantages of ferroelectric than the other variants. High on-current of 175.6 μA/μm and low off-current of 38.4 aA/μm are achieved at t FE of 4 nm through proper utilization of gate-overlap on to the drain side. Furthermore, the proposed MFS structure successfully delivers low average and minimum subthreshold swings even at very thin t FE .
The scope of the work is to investigate limitations in device scaling by identifying various parameters of short channel effects (SCEs) in current challenging geometries of the line tunnel field effect transistors (TF...
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ISBN:
(数字)9781728142326
ISBN:
(纸本)9781728142333
The scope of the work is to investigate limitations in device scaling by identifying various parameters of short channel effects (SCEs) in current challenging geometries of the line tunnel field effect transistors (TFETs). Key factors of the considered device, such as the doping and the thickness (t n ) of n-epitaxial region, and source-to-drain length (L SDeff ) scaling cannot be tuned anymore to boost the device characteristics for the sub-8-nm technology node. The main results of this study indicates that the engineering acceptable performance are achieved at a low doping of 5 × 10 18 cm -3 , an optimal t n as low (about 0.5 nm), and a L SDeff greater than 12.5 nm. Hence, the line TFETs below sub-8-nm faces serious bottleneck of scaling and cannot be further scaled with the conventional scaling rule at all.
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