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2nd International Conference on Convergent Information Technology, ICCIT 07

作者： Gong, Min-Sik Seong, Yeong Rak Lee, Cheol-Hoon System Software Lab. Dept. of Computer Engineering Chungnam National Univ. Yuseong-Gu Daejeon 305-764 Korea Republic of Computer Engineering Lab. School of Electrical Engineering Kookmin Univ. Seoul 136-702 Korea Republic of

ISBN: (纸本)0769530389

The processors supporting the dynamic voltage scaling, called by DVS, have a feature that practically operates with discrete frequency and voltage levels. Almost of DVS algorithms select the smallest frequency level greater than the computed ideal level. Thus the system wastes a computational resource due to under-utilization. In this paper, we present an approach that the task executes its job under two adjacent discrete frequency levels, if possible, instead of the scaling factor computed by On-Line Dynamic Voltage Scaling(OLDVS)[1] under the ideal level. This approach combines discrete DVS feature with OLDVS. So, each task can divide the given time budgets into two parts. Then the task executes its job at the lower frequency/voltage level in the first part. If the task does not complete until the end of the first part, then the scheduler increases the frequency to complete the remaining computation load with the remaining time budgets. Therefore, it can achieve more energy savings than the original OLDVS while simultaneously preserving timeliness guarantees made by real-time scheduling. Simulation results show that OLDVS* provides up to 20% of additional energy savings for Intel PXA250[18] which has four discrete frequency/voltage levels. © 2007 IEEE.

关键词： Voltage scaling

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On-Line Dynamic Voltage Scaling on Processor with Discrete Frequency and Voltage Levels

On-Line Dynamic Voltage Scaling on Processor with Discrete F...

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International Conference on Convergence Information Technology

作者： Min-Sik Gong Yeong Rak Seong Cheol-Hoon Lee System Software Laboratory Department of Computer Engineering Chungnam National University Daejeon South Korea Computer Engineering Laboratory School of Electrical Engineering Kookmin University Seoul South Korea Department of Computer Engineering Chungbuk National University Daejeon South Korea

ISBN: (纸本)9780769530383

The processors supporting the dynamic voltage scaling, called by DVS, have a feature that practically operates with discrete frequency and voltage levels. Almost of DVS algorithms select the smallest frequency level greater than the computed ideal level. Thus the system wastes a computational resource due to under-utilization. In this paper, we present an approach that the task executes its job under two adjacent discrete frequency levels, if possible, instead of the scaling factor computed by on-line dynamic voltage scaling(OLDVS) under the ideal level. This approach combines discrete DVS feature with OLDVS. So, each task can divide the given time budgets into two parts. Then the task executes its job at the lower frequency/voltage level in the first part. If the task does not complete until the end of the first part, then the scheduler increases the frequency to complete the remaining computation load with the remaining time budgets. Therefore, it can achieve more energy savings than the original OLDVS while simultaneously preserving timeliness guarantees made by real-time scheduling. Simulation results show that OLDVS provides up to 20% of additional energy savings for Intel PXA250[18] which has four discrete frequency/voltage levels.

关键词： Dynamic voltage scaling Frequency Voltage control Real time systems Processor scheduling system software Portable computers Clocks Scheduling algorithm Switches

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Cross-Correlation Distribution of p-ary m-Sequence and Its p + 1 Subsequences

Cross-Correlation Distribution of p-ary m-Sequence and Its p...

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IEEE International Symposium on Information Theory

作者： Eun-Young Seo Young-Sik Kim Jong-seon No Dong-Joon Shin School of Electrical Engineering and Computer Science Seoul National University Seoul South Korea Embedded Software Center System LSI Division Samsung Electronics Company Limited Yongin si South Korea Division of Electronics and Computer Engineering Hanyang University Seoul South Korea

ISBN: (纸本)9781424413973;1424413974

For an odd prime p, an even integer n, and d = p k + 1 with gcd(n, k) = 1, there are p + 1 distinct decimated sequences s(dt + l), 0 les I < p + 1, for a p-ary m-sequence s(t) of period p n - 1 since gcd(d, p n -1) = p + 1. In this paper, the cross-correlation distribution between a p-ary m-sequence s(t) and its p+1 distinct decimated sequences s(dt+l) is derived. The maximum magnitude of their cross-correlation values is l+p radic p n if I = 0 mod p + 1 for n = 0 mod 4 or I = (p + l)/2 mod p + 1 for n = 2 mod 4 and otherwise, 1 + radicp n . Also by using s(t) and s(dt + I), a new family of p-ary sequences of period p n -1 is constructed, whose family size is p n middot and C max is 1+ pradicp n .

关键词： computer science Embedded software Distributed computing Embedded computing systems engineering and theory Large scale integration Upper bound Galois fields

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Cross-Correlation Distribution of p-ary m-Sequence of Period p4k - 1 and Its Decimated Sequences by (p2k+1/2)2

Cross-Correlation Distribution of p-ary m-Sequence of Period...

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IEEE International Symposium on Information Theory

For an odd prime p, n=4k, and d=((p 2k +1)/2) 2 , there are (p 2k +1)/ 2 distinct decimated sequences s(dt+l), 0lesl2k+1)/2, of a p-ary m-sequence s(t) of period p n -1 because gcd(d,p n -1)=(p 2k +1)/2. In this paper, it is shown that the cross-correlation function between s(t) and s(dt+I), 0lesl< (p 2k +1)/2, takes the values in {-1, -1 - radicp n , -1+radicp n -1+2radicp n } and their cross-correlation distribution is also derived.

关键词： computer science Embedded software Distributed computing Embedded computing systems engineering and theory Large scale integration Galois fields

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NECESSARY AND SUFFICIENT CONDITIONS FOR DEADLOCKS IN FLEXIBLE MANUFACTURING systemS BASED ON A DIGRAPH MODEL

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Asian Journal of Control 2008年第2期6卷

作者： Wenle Zhang Robert P. Judd Paul Deering School of Electrical Engineering and Computer Science Ohio University Athens OH 45701. Dr. Judd has over twenty years of experience as an educator researcher and consultant in system simulation discrete event controls and systems integration. Dr. Judd has received over thirty research grants totaling over $3500000. His funding has come from both industrial and governmental sources. He is the author or co-author of over a hundred published papers in journals and conferences. He also wrote a book chapter devoted to integrating manufacturing design tools and edited a special issue of the International Journal of Computer Integrated Manufacturing dedicated to intelligent manufacturing systems. Dr. Judd holds a patent on simulation software integration. Russ College of Engineering and Technology Ohio University Athens OH 45701.

As typical discrete event systems, flexible manufacturing systems have been extensively studied in such aspects as modeling, control and performance analysis. One important topic in the study of such systems is the deadlock detection, prevention and avoidance. In the past decade, two major modeling formalisms, i.e., Petri nets and digraphs, have been adopted for developing deadlock control policies for flexible manufacturing systems. In this paper, the concepts of slack, knot, order and effective free space of circuits in the digraph are established and used to concisely and precisely quantify the sufficient conditions for a system state to be live. Necessary conditions for this liveness is quantified for a special class of system states - called evaluation states. The significance of the result is that the conditions are true for avoiding both primary deadlocks and impending deadlocks that are arbitrary steps away from a primary one, whereas only second level deadlocks have been studied in the literature. Examples are provided to illustrate the method.

关键词： Flexible manufacturing systems deadlock avoidance deadlock prevention petri net digraph

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Edge Relaxation in Images using Directional Hierarchical Image Decomposition

Edge Relaxation in Images using Directional Hierarchical Ima...

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Proceedings of the Nordic Signal Processing Symposium (NORSIG)

作者： Dusan Heric Bozidar Potocnik Faculty of Electrical Engineering and Computer Science System Software Laboratory University of Maribor Maribor Slovenia

This paper presents a new hierarchical method of the edge relaxation by using an edge confidence measure. Proposed method is an adaptive and based on directional hierarchical image decomposition and an edge connecting algorithm. It is shown that such combination has low sensitivity to noise, while it is highly robust to outliers, and provide a quality edge connection mechanism

关键词： Image decomposition Image edge detection Image segmentation Image processing Relaxation methods Joining processes Labeling Image analysis computer science system software

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Image enhancement by using directional wavelet transform

Image enhancement by using directional wavelet transform

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International Conference on Information Technology Interfaces

作者： D. Heric B. Potocnik Faculty of Electrical Engineering and Computer Science System Software Laboratory University of Maribor Maribor Slovenia

The purpose of this paper is to introduce a novel image enhancement technique by using directional wavelet transform. Directional wavelet transform decomposes an image into four-dimensional space which augments the image by the scale and directional information. We show the directional information significantly improves image enhancement in noisy images in comparison with the classical techniques. Image enhancement is based on the multiscale singularity detection with an adaptive threshold whose value is calculated via maximum entropy measure. The proposed technique was tested on synthetic images at different signal-to-noise ratios and clinical images

关键词： Image enhancement Wavelet transforms Histograms Laplace equations Image processing Entropy Testing Signal to noise ratio Noise reduction Image analysis

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Multiscale Edge Detector

Multiscale Edge Detector

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International Symposium on Electronics in Marine (ELMAR)

作者： D. Heric B. Potocnik Faculty of Laboratory of Electrical Engineering and Computer Science System Software Laboratory University of Maribor Maribor Slovenia

The purpose of this paper is to introduce an novel edge detector using directional wavelet transform and signal registration. Directional wavelet transform decomposes an image into four-dimensional space which augments the image by the scale and directional information. We show the directional information significantly improves edge detection in noisy images in comparison with the classical multiscale edge detector, and enables more reliable edge tracing along an object boundary. Edge detection is based on the modulus maximum principle with an adaptive threshold whose value is calculated via maximum entropy measure. Edge tracing is done with signal alignment between neighbour edges

关键词： Image edge detection Detectors Wavelet transforms Discrete wavelet transforms Laboratories computer science system software Object detection Entropy Image registration

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Agent Design Patterns Framework for MaSE/POAD Methodology

Agent Design Patterns Framework for MaSE/POAD Methodology

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ACS/IEEE International Conference on computer systems and Applications

作者： R. Mohamad S. Deris H.H. Ammar Software Engineering Department Faculty of Computer Science and Information System Universiti Teknologi Malaysia Johor Malaysia Computer Science and Electrical Engineering Department West Virginia University Morgantown WV USA

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Dynamic voltage scaling for real-time scheduling of multimedia tasks

Dynamic voltage scaling for real-time scheduling of multimed...

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6th Pacific Rim Conference on Multimedia - Advances in Mulitmedia Information Processing - PCM 2005

作者： Seong, Yeong Rak Gong, Min-Sik Oh, Ha Ryoung Lee, Cheol-Hoon Computer Engineering Lab. School of Electrical Engineering Kookmin University Seoul 136-702 Korea Republic of System Software Lab. Dept. of Computer Engineering Chungnam National University Taejeon 305-764 Korea Republic of

ISBN: (纸本)3540300406

Real-time multimedia applications are usually played back many times. For those applications, the distribution of actual execution time is no longer unknown from the second playback. In this paper, we propose a novel dynamic voltage scaling (DVS) algorithm, called CLDVS, for scheduling real-time multimedia applications. In order to minimize energy consumption, CLDVS determines the processor's operating frequency and supply voltage using the distribution of actual execution time during a time interval at the beginning of the interval. For that, all active tasks in the time interval are identified and incrementally placed on the time vs. scaling factor space in order to reduce variations of the scaling factor for minimum energy consumption. Simulation experiments show CLDVS achieves enormous energy savings and outperforms the existing DVS algorithms with different dynamic workload characteristics. © Springer-Verlag Berlin Heidelberg 2005.

关键词： Multimedia systems

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