In the current era of technology,the Internet and web technologies become the center source of *** to the huge amount of contents,one of the main challenges of modern information technology is aimed at how to reduce a...
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In the current era of technology,the Internet and web technologies become the center source of *** to the huge amount of contents,one of the main challenges of modern information technology is aimed at how to reduce and manage information in a structured way with mobilizing users to the similar kind of relevant ***,any intelligent system should be able to understand people's interest about a particular type of information and automatically mobilize him to the similar kind of available information *** idea of high level Activity Streams along with its standardized format can play a vital role to solve this problem in the broader *** paper introduces a novel system called CoASGen (Consolidation and Activity Streams Generator) which is able to automatically generate high level Activity Streams after aggregating and consolidating from different independent systems (*** a software company context:version management system,wikis,bug trackers etc.).It retrieves life time information as heterogeneous web feed by sensing user activities from those independent systems and then it transforms several similar types of atomic activities into high level Activity Streams using semantic technologies along with its specific standardized ***,it shows these high level Activity Streams to the user interface which is able to automatically motivate users to find relevant information easily without either missing any data or losing valuable *** system solves the problem "data silos" by reducing and managing information in a structured way.
State space modeling of Memristor based Wien `A' oscillator has been demonstrated for the first time considering nonlinear ion drift in Memristor. Time dependant oscillating resistance of Memristor is reported in ...
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State space modeling of Memristor based Wien `A' oscillator has been demonstrated for the first time considering nonlinear ion drift in Memristor. Time dependant oscillating resistance of Memristor is reported in both state space solution and SPICE simulation which plausibly provide the basis of realizing parametric oscillation by Memristor based Wien oscillator. In addition to this part Memristor is shown to stabilize the final oscillation amplitude by means of its nonlinear dynamic resistance which hints for eliminating diode in the feedback network of conventional Wien oscillator.
In this paper, we study the effect of the numerical solution accuracy on the digital implementation of differential chaos generators. Four systems are built on a Xilinx Virtex 4 FPGA using Euler, mid-point, and Runge-...
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In this paper, we study the effect of the numerical solution accuracy on the digital implementation of differential chaos generators. Four systems are built on a Xilinx Virtex 4 FPGA using Euler, mid-point, and Runge-Kutta fourth order techniques. The twelve implementations are compared based on the FPGA used area, maximum throughput, maximum Lyapunov exponent, and autocorrelation confidence region. Based on circuit performance and the chaotic response of the different implementations, it was found that less complicated numerical solution has better chaotic response and higher throughput.
This paper introduces the fully digital implementation of a 1-D multiscroll chaos generator based on a staircase nonlinearity in the 3rd-order jerk system using the Euler approximation. For the first time, digital des...
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This paper introduces the fully digital implementation of a 1-D multiscroll chaos generator based on a staircase nonlinearity in the 3rd-order jerk system using the Euler approximation. For the first time, digital design is exploited to provide real-time controllability of (i) number of scrolls, (ii) position in 1-D space, (iii) Euler step size and (iv) system parameter. The effect of variations in these fields on the maximum Lyapunov exponent (MLE) is analyzed. The system is implemented using Verilog HDL and synthesized on an Xilinx Virtex 4 FPGA, exhibiting area utilization less than 3.5% and high performance with experimentally verified throughput up to 3.33 Gbits/s. This fully digital system enables applications in modulation schemes and chaos-based cryptosystems without analog to digital conversion.
Porous Silicon (PS) doped Erbium (Er) has been studied where Er on PSi is involved interaction of silicon and silicon dioxide. The Er doping process was carried out by immersion technique with electrolyte composed of ...
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ISBN:
(纸本)9781467300216
Porous Silicon (PS) doped Erbium (Er) has been studied where Er on PSi is involved interaction of silicon and silicon dioxide. The Er doping process was carried out by immersion technique with electrolyte composed of Erbium (III) nitrate pentahydrate (Er_3NO_3OH_5) and Ethanol. The photoluminescence (PL) effect on PSi samples have been studied and shows a PL intensity is improves at certain mass percentage of Erbium (Er) and the PL peak shifts to the blue luminescence. The result shows that when the Erbium diffuses into a pore, an enhancement of the photoluminescence was obtained for all Erbium used concentration. The photoluminescence of porous silicon (PS) was increased at about 12%. It was also found that the photoluminescence became stable at certain point after the dopant solution continually to increase. All samples show a broad nanocrystal-related luminescence spectrum centered around 700 nm to 725 nm. So it concluded that the porous silicon doped with erbium is able to increase the photoluminescence intensity.
Muslims have genuine concerns regarding origin of the meat at the market. On the other hand, several Muslim countries import meat whose origin is doubtful and bearing an unverifiable HALAL-label. This is because there...
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Muslims have genuine concerns regarding origin of the meat at the market. On the other hand, several Muslim countries import meat whose origin is doubtful and bearing an unverifiable HALAL-label. This is because there is no intelligence device available to check either meat is slaughtered or not? Therefore, the purpose of this study is to determine the values of the dielectric constant of chicken at respective applied frequency of 30.0 Hz, 250.0 KHz and 3.0 MHz. In order to simulate on RC circuit as well as to determine characteristic properties that can differentiate between slaughtered and non-slaughtered chicken using the capacitance measurement technique. The slaughtered and non slaughtered chicken is used as the dielectric medium of the capacitor in the RC circuit. The different values of dielectric constant are obtained from variation of the dielectric medium of the meat as a capacitor. The testing and variation of the capacitance values could determine the status of the meat either slaughtered or not. The results showed that; the frequency of 250 KHz gives stable outputs. In addition, a significant deviation of dielectric constant between slaughtered and non-slaughtered chicken has been observed. The values of dielectric constant of slaughtered chicken appear to be lower than those of non-slaughtered chicken. The result indicates a potential sensing property that able to distinguish between slaughtered and non-slaughtered meat.
Social navigation provides drivers with an advice that aims to shift traffic flows in a network from a user equilibrium to a system optimum. The advice is based on minimizing a combination of the individual travel tim...
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Social navigation provides drivers with an advice that aims to shift traffic flows in a network from a user equilibrium to a system optimum. The advice is based on minimizing a combination of the individual travel time and the marginal total travel time in the network. The level of altruism defines the extent to which a driver is willing to sacrifice his own travel time in favor of other drivers. Fuel consumption and CO2 emission are taking into account by converting them into time equivalent. Experimental results for a small network loosely representing the Bay area show that social navigation can reduce time delays by 10%. The reduction is positively correlated with network load, market penetration and level of altruism.
Real time rendering of three-dimensional scenes in Ray Tracing is a hard problem. However, parallel implementations have been enabling real time performance, as the algorithm can be highly parallelized. Thus, a custom...
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Real time rendering of three-dimensional scenes in Ray Tracing is a hard problem. However, parallel implementations have been enabling real time performance, as the algorithm can be highly parallelized. Thus, a custom parallel design in hardware is likely to achieve a good performance. In this paper, we further improve the GridRT architecture overall performance by embedding the ray-triangle intersection computation into the precessing elements that form the architecture. Low cost and high rendering performance are the main concerns in this novel design. The results show that the execution time of each intersection computation is reduced by at least 50%, while the area cost is practically unchanged or even reduced when compared to the original GridRT implementation.
Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-)co...
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Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-)configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse.
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