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共 144 条记录，以下是91-100 订阅

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Integrated Distributed Transversal Filters for Pulse Shaping and Interference Suppression in UWB Impulse Radios

Integrated Distributed Transversal Filters for Pulse Shaping...

引用

IEEE International Conference on Ubiquitous Wireless Broadband (ICUWB)

作者： Yunliang Zhu Hui Wu Laboratory for Advanced Integrated Circuits and Systems Department of Electrical and Computer Engineering University of Rochester Rochester NY USA

The stringent emission mask and interference specifications in ultra-wideband (UWB) impulse radios present great challenges for the transceiver architecture design and circuit implementation. This paper proposes to use integrated distributed transversal filters (DTF) for pulse shaping in the transmitter and for narrow-band interference (NBI) suppression in the receiver. Analyses show that an integrated DTF can accurately generate notches at multiple frequencies with tunability and relatively low power consumption. A 7-tap DTF prototype was implemented using a commercial 0.18 mum SiGe BiCMOS technology. Measurement results demonstrate the pulse shaping and interference suppression capabilities of DTFs. The typical power consumption of the prototype is 30 mW

关键词： Transversal filters Pulse shaping methods Interference suppression Energy consumption Prototypes Ultra wideband technology Transceivers circuits Radio transmitters Narrowband

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A 10-40 GHz 7 dB Directional Coupler in Digital CMOS Technology

A 10-40 GHz 7 dB Directional Coupler in Digital CMOS Technol...

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Microwave, MTT-S International Symposium

作者： Yunliang Zhu Hui Wu Laboratory for Advanced Integrated Circuits and Systems Department of Electrical and Computer Engineering University of Rochester Rochester NY USA

We present an integrated wideband directional coupler for millimeter-wave applications implemented in low-cost silicon technologies. It is constructed using broad-side coupled coplanar waveguides (CPW), taking advantage of available multiple metal layers in silicon technologies. A prototype coupler was designed and fabricated using a commercial 0.18mu digital CMOS technology with low-resistivity epi substrate. It achieves a 10-40 GHz frequency range (3-dB bandwidth) with 7 dB to 10 dB coupling and more than 10 dB directivity. Measurement results match well with electromagnetic simulation

关键词： CMOS technology Directional couplers Millimeter wave technology Silicon Coplanar waveguides Wideband Electromagnetic waveguides Prototypes Frequency Bandwidth

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A new structure for capacitor-mismatch-insensitive multiply-by-two amplification

A new structure for capacitor-mismatch-insensitive multiply-...

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IEEE International Symposium on circuits and systems (ISCAS)

作者： H. Zare-Hoseini O. Shoaei I. Kale Applied DSP and VLSI Research Group Department of Electronic Systems University of Westminster London UK IC Design Laboratory Electrical and Computer Engineering Department University of Tehran Tehran Iran KKTC Eastern Mediterranean University Gazi Magusa Mersin Turkey

A new approach to achieve a switched-capacitor multiply-by-two gain-stage with reduced sensitivity to capacitors' mismatches is presented in this paper. It is based on sampling fully differential input signals onto both plates of the input capacitors rather than sampling onto one plate of the capacitors with the other tied to a reference. It uses one operational amplifier (op-amp) in two phases to produce the gain of two (times2). Comparing to the conventional multiply-by-two gain-stage, the mismatches between the capacitors has a much smaller influence on the accuracy of the gain of two (times2). Analytical and circuit-level analysis of the architecture and the conventional structure are presented using a generic 0.35mum CMOS technology

关键词： Capacitors Operational amplifiers Sampling methods Digital signal processing Very large scale integration Feedback Circuit analysis Energy consumption Transfer functions Voltage

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High speed systems engineering: A new trent in electrical and computer engineering

High speed systems engineering: A new trent in electrical an...

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2005 ASEE Annual Conference and Exposition: The Changing Landscape of engineering and Technology Education in a Global World

作者： Mina, Mani Weber, Robert Somani, Arun K. VanderHorn, Nathan Bahuguna, Rashmi High Speed Systems Engineering Laboratory Department of Electrical and Computer Engineering Iowa State University United States Iowa State University United States Analog and Mixed-Signal VLSI Design Center United States

The main ideas and objectives of High Speed systems engineering (HSSE) are presented. HSSE is being used as integrating pedogogical and research platforms to train modern engineers and future researchers. The newly developed classes and the changes made in the curriculum is enhancing interaction between faculty, graduate and undergraduate students. A study shows that HSSE has been successful in encouraging students from all undergraduate levels to participate in learning and experimenting, also are encouraged to be involved in research and graduate studies.

关键词： systems engineering

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2.40-2.48 GHz bandpass filter in 0.18 /spl mu/m CMOS

2.40-2.48 GHz bandpass filter in 0.18 /spl mu/m CMOS

引用

IEEE International Workshop on Radio-Frequency Integration Technology (RFIT)

作者： R.C. Yadav K.S. Lee V. Bharadwaj Integrated Circuits and Systems Laboratory Institute of Microelectronics Singapore Department of Electrical and Computer Engineering National University of Singapore Singapore

A band-pass filter operating in 2.40 GHz to 2.48 GHz range is designed in 0.18 /spl mu/m CMOS technology. It has tunable center frequency, Q-factor and gain. The fully integrated system-on-chip (SOC) 10th order band-pass filter is built by cascading five stages of 2nd order. The simulation of the filter on ADS software provides an insertion gain of 8 dB in the pass-band frequency from 2.40 GHz to 2.48 GHz. The attenuation in the stop-band is observed to be higher than 50 dB at 400 MHz away from pass-band edge with 15 mA current sinking from a 1.8 V supply. We present several simulation results to highlight these characteristics.

关键词： Band pass filters Frequency circuits MOSFETs Inductors Q factor CMOS technology Impedance Reflection Resistors

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Minimization of secondary effects in SOI: a 32-bit ANT logic adder implementation

Minimization of secondary effects in SOI: a 32-bit ANT logic...

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Midwest Symposium on circuits and systems (MWSCAS)

作者： A. Wasson Dipti Sanghvi A. Nunez VLSI Systems Design and CAD (VSDCAD) Laboratory Department of Electrical Engineering and Computer Science (EECS) Syracuse University Syracuse NY USA

This paper presents a review of circuit design techniques related to silicon on insulator technology (SOI) CMOS circuits. The most important design considerations are parasitic bipolar effect, floating body effect and hysteric variation in the threshold voltage. These effects lead to the reduction of the noise margin and under serious circumstances may lead to a wrong output. Dynamic circuits are most vulnerable to these effects due to the presence of a soft node at the top of the pull down stack. We have studied the various existing techniques and have proposed a design modification which alleviates the floating body effect without compromising other parameters like speed and without penalizing the charge sharing present. The approach is based on adding an extra transistor which will minimize the floating body effect without worsening charge sharing. The effectiveness of our design technique is demonstrated through its implementation in a 32-bit ANT logic carry look ahead adder using BSIMSOI models. Results show that the performance of the modified circuit is reliable and minimizes the floating body effect without adversely affecting charge sharing

关键词： Minimization Silicon on insulator technology Adders CMOS logic circuits Circuit synthesis CMOS technology Threshold voltage Noise reduction Circuit noise Logic design

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Pre-layout parasitic estimation in interconnects

Pre-layout parasitic estimation in interconnects

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Midwest Symposium on circuits and systems (MWSCAS)

作者： S. Shah A. Nunez Department of Electrical Engineering and Computer Science (EECS) VLSI Systems Design and CAD (VSDCAD) Laboratory Syracuse University Syracuse NY USA

Interconnect lengths have become a dominant factor in the design of integrated circuits. The parasitics associated with the interconnects account for a significant part of signal delay. The estimation of interconnect lengths prior to placement helps in determining the delay early in the design phase. In this paper, a methodology to estimate the interconnect lengths prior to layout, is presented. The approach is heuristics based. Various layouts have been studied to observe typical placement and routing patterns. The methodology uses the gate level netlist and properties of the cells obtained from the standard cell libraries for the estimation. The results have been compared with the detailed routing wire lengths obtained after synthesis of the gate level netlist. Cadence Buildgates was used for syntheises and Cadence Encounter used for placement and routing of the circuits. The methodology presented is independent of the technology being used. However the wire lengths will vary with the use of different placement and routing tools

关键词： Integrated circuit interconnections Wire Delay estimation Routing Circuit synthesis Capacitance Libraries Optimization methods Pins Very large scale integration

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Processor allocation for tasks that is robust against errors in computation time estimates

Processor allocation for tasks that is robust against errors...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： P.V. Sugavanam H.J. Siegel A.A. Maciejewski S.A. Ali M. Al-Otaibi M. Aydin K. Guru A. Horiuchi Y.G. Krishnamurthy P. Lee A. Mehta O. Oltikar R. Pichel A.J. Pippin M. Raskey V. Shestak J. Zhang Department of Electrical & Computer Engineering Colorado State University Fort Collins CO USA Department of Electrical & Computer Engineering Department of Computer Science Colorado State University Fort Collins CO USA Systems & VLSI Technology Division Hewlett Packard Company Fort Collins CO USA Linux & Open Source Laboratory Colorado State University Fort Collins CO USA School of Computer Science Salt Lake UT USA

Heterogeneous computing systems composed of interconnected machines with varied computational capabilities often operate in environments where there may be sudden machine failures, higher than expected load, or inaccuracies in estimation of system parameters. Makespan (defined as the completion time for an entire set of tasks) is often the performance feature that is optimized in such systems. It is important that the makespan of a resource allocation (mapping) be robust against errors in task computation time estimates. The problem of optimally mapping tasks onto machines of a heterogeneous computing environment has been shown, in general, to be NP-complete. Therefore, heuristic techniques to find near optimal solutions to this mapping problem are required. The goal of this research is to find a static mapping of tasks so that the robustness of the desired system feature, makespan, is maximized against the errors in task execution time estimates. Seven heuristics to derive near-optimal solutions and an upper bound to this problem are presented and evaluated.

关键词： Robustness Resource management State estimation Parameter estimation Educational technology Production computer science Active appearance model Very large scale integration Linux

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Cost-effective video filtering solution for real-time vision systems

Cost-effective video filtering solution for real-time vision...

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作者： Fischer, Viktor Lukac, Rastislav Martin, Karl Laboratoire Traitement du Signal et Instrumentation Unité Mixte de Recherche CNRS 5516 Université Jean Monnet 10 rue Barrouin 42000 Saint-Etienne France Multimedia Laboratory Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto 10 King's College Road Toronto Ont. M5S 3G4 Canada Jean Monnet University of Saint-Etienne France Department of Electronics and Computer Science Micronic Košice Slovakia Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto Toronto Canada IEEE Circuits and Systems IEEE Consumer Electronics IEEE Signal Processing Societies IEEE Signal Processing Society Communications Society

This paper presents an efficient video filtering scheme and its implementation in a field-programmable logic device (FPLD). Since the proposed nonlinear, spatiotemporal filtering scheme is based on order statistics, its efficient implementation benefits from a bit-serial realization. The utilization of both the spatial and temporal correlation characteristics of the processed video significantly increases the computational demands on this solution, and thus, implementation becomes a significant challenge. Simulation studies reported in this paper indicate that the proposed pipelined bit-serial FPLD filtering solution can achieve speeds of up to 97.6 Mpixels/s and consumes 1700 to 2700 logic cells for the speed-optimized and area-optimized versions, respectively. Thus, the filter area represents only 6.6 to 10.5% of the Altera STRATIX EP1S25 device available on the Altera Stratix DSP evaluation board, which has been used to implement a prototype of the entire real-time vision system. As such, the proposed adaptive video filtering scheme is both practical and attractive for real-time machine vision and surveillance systems as well as conventional video and multimedia applications.

关键词： computer vision

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Robust Processor Allocation for Independent Tasks When Dollar Cost for Processors is a Constraint

Robust Processor Allocation for Independent Tasks When Dolla...

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IEEE International Conference on Cluster Computing

作者： Prasanna Sugavanam H. J. Siegel Anthony A. Maciejewski Junxing Zhang Vladimir Shestak Michael Raskey Alan Pippin Ron Pichel Mohana Oltikar Ashish Mehta Panho Lee Yogish Krishnamurthy Aaron Horiuchi Kumara Guru Mahir Aydin Mohammad Al-Otaibi Syed Ali Department of Electrical & Computer Engineering Colorado State University USA Colorado State University Fort Collins CO US School of Computing University of Utah Salt Lake UT USA Linux & Open Source Laboratory Hewlett Packard Company USA Systems & VLSI Technology Division Hewlett Packard Company Fort Collins CO USA

In a distributed heterogeneous computing system, the resources have different capabilities and tasks have different requirements. Different classes of machines used in such systems typically vary in dollar cost based on their computing efficiencies. Makespan (defined as the completion time for an entire set of tasks) is often the performance feature that is optimized. Resource allocation is often done based on estimates of the computation time of each task on each class of machines. Hence, it is important that makespan be robust against errors in computation time estimates. The dollar cost to purchase the machines for use can be a constraint such that only a subset of the machines available can be purchased. The goal of this study is to: (1) select a subset of all the machines available so that the cost constraint for the machines is satisfied, and (2) find a static mapping of tasks so that the robustness of the desired system feature, makespan, is maximized against the errors in task execution time estimates. Six heuristic techniques to this problem are presented and evaluated

关键词： Robustness Costs Resource management Distributed computing Educational technology System performance Degradation computer science Active appearance model Cities and towns

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