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IEEE computer Society Annual Symposium on vlsi

作者： Hua Tang Hui Zhang A. Doboli VLSI Systems Design Laboratory Electrical and Computer Engineering Department State University of New York Stony Brook NY USA

ISBN: (纸本)0769519040

This paper presents a new methodology for layout-aware synthesis of analog systems. The methodology combines block parameter exploration, block placement and global interconnect routing while maintaining an accurate perspective on the layout parasitics. An original system representation (called Layout Constraint Graphs - LCG) was developed for synthesis. The paper discusses how block parameter exploration, placement and global routing are expressed in terms of the LCG graph. AC and transient performances of each explored solution are obtained using SPICE simulations. Experiments show the generality of the synthesis methodology by providing results for several applications including filters and converters.

关键词： Routing Signal synthesis Circuit synthesis Design optimization Circuit simulation Wire Laboratories Integrated circuit interconnections SPICE Design automation

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Piecewise-linear modeling of analog circuits using trained feed-forward neural networks and adaptive clustering of hidden neurons

Piecewise-linear modeling of analog circuits using trained f...

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International Joint Conference on Neural Networks (IJCNN)

作者： S. Doboli G. Gothoskar A. Doboli Computer Science Department Hofstra University Hempstead NY USA VLSI Systems Design Laboratory Electrical and Computer Engineering Department SUNY Stony Brook Stony Brook NY USA

This paper presents a new technique for automatically creating analog circuit models. The method extracts piecewise linear models from trained neural networks. A model is a set of linear dependencies between circuit performances and design parameters. The paper illustrates the technique for an OTA circuit - an amplifier circuit widely used in filters and A/D converters for which models for gain and bandwidth were automatically generated. As experiments show, the obtained models have simple form that accurately fits the sampled points and the behavior of the trained neural networks. These models are useful for fast simulation of systems with non-linear behavior and performances.

关键词： Piecewise linear techniques Analog circuits Feedforward systems Neural networks Feedforward neural networks Adaptive systems Neurons Filters Bandwidth Circuit simulation

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BIST-based delay-fault testing in FPGAs

BIST-based delay-fault testing in FPGAs

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IEEE International On-Line Testing Workshop

作者： M. Abramovici C. Stroud Circuits and Systems Research Laboratory Agere Systems Murray Hill NJ USA Department of Electrical and Computer Engineering University of North Carolina Charlotte USA

We present the first delay-fault testing approach for FPGAs, applicable both for manufacturing and for on-line testing. Our approach is based on BIST, is comprehensive, and does not require expensive ATE. We have succ... 详细信息

关键词： Delay Field programmable gate arrays Circuit testing Built-in self-test Manufacturing Logic testing Clocks Frequency Circuit faults Application specific integrated circuits

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State space blind source recovery for mixtures of multiple source distributions

State space blind source recovery for mixtures of multiple s...

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IEEE International Symposium on circuits and systems (ISCAS)

作者： K. Waheed F.M. Salam Circuits Systems and Artificial Neural Networks Laboratory Department of Electrical and Computer Engineering Michigan State University East Lansing MI USA

The paper discusses state space blind source recovery (BSR) for minimum phase and non-minimum phase mixtures of Gaussian and non-Gaussian distributions. The state space natural gradient approach results in compact iterative update laws for BSR. Two separate state space algorithms for minimum phase and non-minimum phase mixing environments are presented. The advantages and disadvantages of both algorithms in the context of multiple source distribution mixtures are examined. The presented BSR algorithms require use of nonlinearities, which depend on the distribution of the unknown sources. We propose use of an adaptive nonlinearity based on the batch kurtosis of the output. This renders the adaptive estimation of the demixing network completely blind.

关键词： State-space methods Signal processing algorithms Iterative algorithms Gaussian distribution circuits Artificial neural networks Laboratories Iterative methods Adaptive estimation Adaptive signal processing

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BIST-based diagnosis of FPGA interconnect

BIST-based diagnosis of FPGA interconnect

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IEEE International Test Conference

作者： C. Stroud J. Nall M. Lashinsky M. Abramovici Department of Electrical and Computer Engineering North Carolina State University Charlotte USA Circuits and Systems Research Laboratory Agere Systems Murray Hill NJ USA

We present a Built-In Self-Test (BIST)-based diagnostic approach for the programmable interconnect resources in Field Programmable Gate Arrays (FPGAs) that can be used for either on-line or off-line testing. The technique was originally intended for on-line diagnosis of faulty interconnect to support fault-tolerant applications. However, the technique has been proven to be an excellent approach for off-line testing and diagnosis as well, providing high-resolution diagnostics with the ability to identify the faulty wire segment or programmable switch. We have implemented this BIST-based diagnostic approach on the ORCA series FPGA and present the results of testing and diagnosing known defective FPGAs.

关键词： Field programmable gate arrays Circuit faults Fault diagnosis Integrated circuit interconnections Built-in self-test System testing Routing Wire Switches Circuit testing

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Piecewise-linear modeling of analog circuits based on model extraction from trained neural networks

Piecewise-linear modeling of analog circuits based on model ...

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IEEE International Workshop on Behavioral Modeling and Simulation (BMAS)

作者： G. Gothoskar A. Doboli S. Doboli VLSI Systems Design Laboratory Electrical and Computer Engineering Department State University of New York Stony Brook Stony Brook NY USA Department of Computer Science Hofstra University Hempstead NY USA

This paper presents a new technique for automatically creating analog circuit models. The method extracts piecewise linear models from trained neural networks. A model is a set of linear dependencies between circuit performance and design parameters. The paper illustrates the technique for an OTA circuit for which models for gain and bandwidth are generated. As experiments show, the obtained models have simple form that accurately fits the sampled points. These models are useful for fast simulation of systems with nonlinear behavior and performance.

关键词： Piecewise linear techniques Analog circuits Neural networks Circuit synthesis Laboratories Predictive models Very large scale integration Analog computers computer networks Design engineering

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Considering the alternatives in low-power design

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IEEE circuits and Devices Magazine 2001年第4期17卷 23-29页

作者： Stouraitis, T. Paliouras, V. Department of Electrical and Computer Engineering University of Patras Greece IEEE Circuits and Systems Society Technical Committee on VLSI Systems and Applications Digital Signal Processing and the Multimedia Systems Committees United States VLSI Design Laboratory ECE Dept. University of Patras Greece Computer Engineering and Informatics Department University of Patras Greece ACM SIAM Technical Chamber of Greece Greece

Recent advances in computer arithmetic offer interesting alternative solutions for low-power design. Depending on an assortment of factors that need to be considered, it is worth evaluating the logarithmic number system (LNS) or the residue number system (RNS) for hardware implementations of computationally intensive tasks. As such, the choice of arithmetic can lead to substantial power savings.

关键词： Integrated circuit layout

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130 Gsample/s photonic analog to digital converter

130 Gsample/s photonic analog to digital converter

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2001 International Topical Meeting on Microwave Photonics, MWP 2001

作者： Bhushan, A.S. Kelkar, P.V. Jalali, B. Boyraz, O. Islam, M. Optoelectronic Circuits and Systems Laboratory Department of Electrical Engineering University of California Los Angeles Los AngelesCA90095-1594 United States Electrical Engineering and Computer Science Department University of Michigan Ann ArborMI48109 United States

ISBN: (纸本)0780370031

Digital processing of the received signals in radar systems leads to higher performance and the ability to rapidly reconfigure such systems. Typically, the analog-to-digital converter (ADC) is the major bottleneck in realizing the digital receiver. Time stretch (TS) preprocessing is a new photonic based approach that can potentially boost the capability of the available electronic ADCs (Coppinger et al, 1999;Bhushan et al, 2000). In this approach, the analog signal is imposed on a chirped optical carrier using an electro-optic modulator. This time to wavelength mapped signal is then dispersed and hence stretched in time prior to digitization by the electronic ADC. Time stretching increases the effective sampling rate and input bandwidth of the ADC. We demonstrate a photonic ADC with a time stretch preprocessor. The system has a sampling rate of 130 GSa/s and a signal-to-noise ratio exceeding 7 effective number of bits. © 2001 IEEE.

关键词： Analog to digital conversion

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A mixed mode neuro-vlsi chip for high speed applications

A mixed mode neuro-VLSI chip for high speed applications

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Midwest Symposium on circuits and systems (MWSCAS)

作者： K. Waheed F.M. Salam Circuits Systems And Neural Networks Laboratory Department of Electrical and Computer Engineering Michigan State University East Lansing MI USA

ISBN: (纸本)078037150X

This paper presents selected design and operation details of a custom integrated neural chip. This neural processing chip is designed in the recent 0.18 /spl mu/m, single poly, six-layer Cu interconnect technology. The chip realizes an architecture that achieves the task of autonomous-learning execution times in micro to milli seconds. The core consists of basic building blocks of 4-quadrant multipliers, transconductance amplifiers, and active load resistances, for analog (forward) network processing and learning modules. Super-imposed on the processing network are digital memory and control modules composed of D-Flipflops, ADC, Multiplying D/A Converter (MDAC), decoders, multiplexers and comparators for parameter (weight) storage, logical control and analog/digital conversions.

关键词： Copper Integrated circuit interconnections Very large scale integration Neural networks Process design LAN interconnection Communication system control Testing Application software Laboratories

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On-line BIST and diagnosis of FPGA interconnect using roving STARs

On-line BIST and diagnosis of FPGA interconnect using roving...

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IEEE International On-Line Testing Workshop

作者： C. Stroud M. Lashinsky J. Nall J. Emmert M. Abramovici Department of Electrical and Computer Engineering University of North Carolina Charlotte USA Agere Systems Circuits and Systems Research Laboratory Murray Hill NJ USA

ISBN: (纸本)0769512909

Presents the first on-line BIST and BIST-based diagnostic approach for the programmable interconnect resources in FPGAs. This interconnect BIST is used in the roving STARs approach. The technique provides a complete BIST of the programmable interconnect followed by high-resolution diagnostics to support reconfiguration around the fault for fault-tolerant applications. We have successfully implemented this BIST approach on the ORCA 2C series FPGA and present the results of testing and diagnosing known defective FPGAs.

关键词： Built-in self-test Field programmable gate arrays Circuit faults Integrated circuit interconnections Routing Fault tolerance System testing Hardware Logic testing Fault detection

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