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检索条件"机构=Electrical and Computer Engineering Department VLSI Circuits and Systems Laboratory"

共 144 条记录，以下是121-130 订阅

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On-line BIST and diagnosis of FPGA interconnect using roving STARs

On-line BIST and diagnosis of FPGA interconnect using roving...

引用

IEEE International On-Line Testing Workshop

作者： C. Stroud M. Lashinsky J. Nall J. Emmert M. Abramovici Department of Electrical and Computer Engineering University of North Carolina Charlotte USA Agere Systems Circuits and Systems Research Laboratory Murray Hill NJ USA

ISBN: (纸本)0769512909

Presents the first on-line BIST and BIST-based diagnostic approach for the programmable interconnect resources in FPGAs. This interconnect BIST is used in the roving STARs approach. The technique provides a complete BIST of the programmable interconnect followed by high-resolution diagnostics to support reconfiguration around the fault for fault-tolerant applications. We have successfully implemented this BIST approach on the ORCA 2C series FPGA and present the results of testing and diagnosing known defective FPGAs.

关键词： Built-in self-test Field programmable gate arrays Circuit faults Integrated circuit interconnections Routing Fault tolerance System testing Hardware Logic testing Fault detection

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Integrated hardware-software co-synthesis and high-level synthesis for design of embedded systems under power and latency constraints

Integrated hardware-software co-synthesis and high-level syn...

引用

Design, Automation and Test in Europe Conference and Exhibition

作者： A. Doboli VLSI Systems Design Laboratory Department of Electrical and Computer Engineering State University of New York Stony Brook Stony Brook NY USA

ISBN: (纸本)0769509932

This paper presents an integrated approach to hardware software co-synthesis and HLS for design of low-power embedded systems. The main motivation for this work is that fine trade-offs between latency and power can be explored at the system level only with a detailed knowledge of used hardware resources. Integrated method was realized as a simulated annealing based solution-space exploration. Exploration is guided by Performance Models, that exactly capture the relationship between performances i.e. power consumption and latency and design decisions i.e. binding and scheduling. The proposed approach permits nor only a more accurate latency and power estimation but also the exposure of RTL-level design decisions at the system level. As a result, more effective power-latency trade-offs are possible during co-synthesis as compared to traditional task-level methods.

关键词： High level synthesis Embedded system Delay Hardware Power system modeling Energy consumption Very large scale integration Laboratories Embedded software Annealing

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Integrated hardware-software co-synthesis for design of embedded systems under power and latency constraints 01

Integrated hardware-software co-synthesis for design of embe...

引用

Proceedings of the conference on Design, automation and test in Europe

作者： A. Doboli VLSI Systems Design Laboratory Department of Electrical and Computer Engineering State University of New York (SUNY) at Stony Brook Stony Brook NY

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Roving STARs: an integrated approach to on-line testing, diagnosis, and fault tolerance for FPGAs in adaptive computing systems

Roving STARs: an integrated approach to on-line testing, dia...

引用

NASA/DoD Workshop on Evolvable Hardware

作者： M. Abramovici J.M. Emmert C.E. Stroud Agere Systems Circuits and Systems Research Laboratory Murray Hill NJ USA Department of Electrical & Computer Engineering University of North Carolina Charlotte Charlotte NC USA

ISBN: (纸本)0769511805

We present an integrated approach to on-line FPGA testing, diagnosis and fault tolerance, to be used in high-reliability and high-availability hardware. The testing and diagnostic process takes place in Self-Testing AReas (STARs) of the FPGA, without disturbing the normal system operation. The entire chip is tested by roving the STARs across the FPGA. Our approach guarantees complete testing of both logic cells and interconnect with maximum diagnostic resolution. Our multi-level fault-tolerant technique allows using partially defective logic and routing resources for normal operation, providing longer mission life in the presence of faults. In addition, our dynamic fault-tolerant method ensures that spare resources are always present in the neighborhood of the located fault, thus simplifying fault-bypassing. Our complete method has been successfully implemented and demonstrated on the ORCA 2CA series FPGAs from Lucent Technologies.

关键词： Fault diagnosis Fault tolerance Field programmable gate arrays Logic testing System testing Circuit testing Automatic testing Fault tolerant systems Programmable control Runtime

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Kalman-filtering timing recovery scheme for orthogonal frequency domain multiplexing (OFDM) systems 25

Kalman-filtering timing recovery scheme for orthogonal frequ...

引用

25th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2000

作者： Hajirostam, Mohamad Maddah-Ali, M.A. Haft-Baradaran, A. Kilani, M.T. Fakhraie, S.M. Sharif-Khani, M. Shoaei, O. VLSI Circuits and Systems Laboratory Department of Electrical and Computer Engineering University of Tehran Tehran Iran

ISBN: (纸本)0780362934

This paper describes a new technique for timing synchronization in orthogonal frequency domain multiplexing (OFDM) transceiver systems. The proposed technique is based on non-synchronized sampling rate and no pilot is required to be transmitted. Therefore the transmission capacity is increased. The proposed algorithm employs the angles of the received symbols in the OFDM subchannels and provides a computationally efficient technique for estimation of the timing error. An equivalent state space model is also derived for timing error and then Kalman filtering method is exploited for tracking purposes. The proposed technique is very robust, particularly under low signal to noise ratio conditions and has been verified by means of computer simulations. © 2000 IEEE.

关键词： Timing circuits

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A rail-to-rail, constant-G/sub m/, 1-volt CMOS opamp

A rail-to-rail, constant-G/sub m/, 1-volt CMOS opamp

引用

IEEE International Symposium on circuits and systems (ISCAS)

作者： F. Bahmani S.M. Fakhraie A. Khakifirooz Electrical and Computer Engineering Department VLSI Circuits and Systems Laboratory University of Tehran Iran

A rail-to-rail, constant-g/sub m/, 1-volt only, full-CMOS opamp is presented. The opamp has a complementary PMOS/bulk-driven input stage with a feedback circuit to equalize g/sub m/, and a class AB output stage, which provide input and output rail-to-rail operation. HSPICE simulations are performed using BSIM 3.3 models of a 0.8 /spl mu/m CMOS process. This opamp has a DC gain of 45.1 dB, unity-gain bandwidth of 1.7 MHz, and phase margin of 63.4/spl deg/.

关键词： Feedback circuits Semiconductor device modeling MOSFETs Rail to rail operation Analog circuits Threshold voltage Very large scale integration Circuit simulation CMOS process Bandwidth

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Kalman-filtering timing recovery scheme for orthogonal frequency domain multiplexing (OFDM) systems

Kalman-filtering timing recovery scheme for orthogonal frequ...

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International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： M. Hajirostam M.A. Maddah-Ali A. Haft-Baradaran M.T. Kilani S.M. Fakhraie M. Sharif-Khani O. Shoaei VLSI Circuits and Systems Laboratory Department of Electrical and Computer Engineering University of Tehran Tehran Iran

关键词： Timing OFDM computer errors Frequency synchronization Frequency domain analysis Transceivers Sampling methods State-space methods Kalman filters Filtering

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Algorithmic design of a 900MHz CMOS RF power amplifier using SPICE-Smith chart method

Algorithmic design of a 900MHz CMOS RF power amplifier using...

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25th European Solid-State circuits Conference, ESSCIRC 1999

作者： Kheirkhahi, A. Fakhraie, S.M. Kamareie, M. VLSI Circuits and Systems Laboratory Dept. of Electrical and Computer Engineering University of Tehran Iran

An algorithmic method for power amplifier design named "SPICE-Smith chart" is introduced and is proved to be accurate and fast. A 900 MHz CMOS fully differential class E PA is designed in a 0.8-μm CMOS process by using this method. This PA has controllable output power in the range of 20-3OdBm with steps of no more than 2.5dB and its maximum PAE is 55%. The output power is controlled by varying the supply voltage of the PA. A Δ-modulated switching power supply, which uses a programmable capacitance array (PCA), is designed to control the supply voltage of the PA. © 1999 Editions Frontieres.

关键词： Capacitance

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Algorithmic design of a 900MHz CMOS RF power amplifier using SPICE-Smith chart method

Algorithmic design of a 900MHz CMOS RF power amplifier using...

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European Conference on Solid-State circuits (ESSCIRC)

作者： A. Kheirkhahi S.M. Fakhraie M. Kamareie VLSI Circuits and Systems Laboratory Department of Electrical and Computer Engineering University of Tehran Iran

An algorithmic method for power amplifier design named "SPICE-Smith chart" is introduced and is proved to be accurate and fast. A 900 MHz CMOS fully differential class E PA is designed in a 0.8-µm CMOS process by using this method. This PA has controllable output power in the range of 20-3OdBm with steps of no more than 2.5dB and its maximum PAE is 55%. The output power is controlled by varying the supply voltage of the PA. A Δ-modulated switching power supply, which uses a programmable capacitance array (PCA), is designed to control the supply voltage of the PA.

关键词： Algorithm design and analysis Radio frequency Power amplifiers Radiofrequency amplifiers CMOS process Power generation Voltage control Power supplies Capacitance Principal component analysis

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Implementation of serial port interconnections for integrated circuits

Implementation of serial port interconnections for integrate...

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International Conference on Microelectronics, ICM

作者： M.R. Samady M.R. Movahedin M. Fakhraie A. Zakeri A. Gholanbar-Dezfuli Iran Electronic Industries Iran Communication Industries (SAMA) Iran Department of Electrical and Computer Engineering VLSI Circuits & Systems Laboratory University of Tehran Iran

Serial ports are used in different equipment and in integrated circuits for data transfer. In this paper, three different types of serial ports are introduced, and then their design, simulation and synthesis on differ... 详细信息

关键词： Integrated circuit interconnections Clocks Transmitters Communication standards Shift registers Logic Digital signal processing Frequency synchronization Communication industry Electronics industry

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