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A 915MHz $19\mu \mathrm{W}$ Blocker-Enhanced Wake-Up Receiver with Frequency-Hopping Two-Tone Modulation Achieving 53dB Tolerance to In-Band Interference

A 915MHz $19\mu \mathrm{W}$ Blocker-Enhanced Wake-Up Receive...

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IEEE Symposium on Radio Frequency Integrated circuits (RFIC)

作者： Heyu Ren Dawei Ye Binbin Chen Xu Jin Wenjun Gong Rongjin Xu C.-J. Richard Shi State Key Laboratory of ASIC and System Fudan University China Institute of Brain-inspired Circuits and Systems (iBiCAS) Fudan University China Department of Electrical and Computer Engineering University of Washington USA

ISBN: (数字)9781665496117

ISBN: (纸本)9781665496124

A 915MHz ultra-low-power blocker-enhanced wake- up receiver (BE-WuRx) is presented in a 65nm CMOS process. Employing the proposed frequency-hopping two-tone modulation (FH-TTM), the BE-WuRx can dynamically convert the in-band blocker power to data power, and achieves a −63.6dBm sensitivity without blocker and a −90dBm enhanced sensitivity with a −25dBm CW interferer, while just consuming $\mathbf{19}\mathbf{\mu}\mathbf{W}$ . With the −63.6dBm sensitivity, the BE-WuRx performs 53dB tolerance to the in-band blocker, exhibiting 14dB improvement compared to the case that FH- TTM is off. The wake-up latency is 6.4ms for a quiet channel and 6.4 to 64ms for a congested channel.

关键词： Sensitivity Frequency modulation Amplitude shift keying Receivers Interference Frequency conversion CMOS process

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MemMIMO: A Simulation Framework for Memristor-Based Massive MIMO Acceleration

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IEEE Transactions on computer-Aided Design of Integrated circuits and systems 2025年

作者： Xu, Jiawei Zheng, Yi Stathis, Dimitrios Wang, Ruijia Shen, Ruisi Zheng, Li-Rong Zou, Zhuo Hemani, Ahmed University of Macau State-Key Laboratory of Analog and Mixed-Signal VLSI Institute of Microelectronics Faculty of Science and Technology ECE Department China Fudan University State Key Laboratory of Integrated Chips and Systems School of Information Science and Technology Shanghai China KTH Royal Institute of Technology School of Electrical Engineering and Computer Science Stockholm Sweden

Memristor-based crossbar architectures have proven highly effective for matrix vector multiplication (MVM) operations, making them a promising solution for accelerating the MVMs widely used in precoding algorithms for multiple input multiple output (MIMO) wireless communication systems. However, real-world implementation of memristor-based computing systems face challenges due to commonly observed non-idealities in both the devices themselves and the circuits they’re built into. To facilitate a rapid design flow and investigate the impact of non-idealities, an integrated open-source simulation framework MemMIMO is developed. The simulation framework estimates the accuracy and hardware performance of the computing system, offering a variety of flexible design options. MemMIMO integrates a behavioral model of the mix-signal architecture with a digital front-end. There are three major building blocks in MemMIMO: the device fitting block, the mapping block, and the performance estimation block. These blocks work together to map the complex MVMs in precoding algorithms for MIMO systems to crossbar-based architectures that incorporate memristor models characterized by physical device behavior. Using two typical use cases targeting six-generation (6G) massive MIMO communication as case studies, MemMIMO is used to model different memristor devices, explore the impact of non-idealities on system accuracy, and benchmark circuit-level performance metrics including area, speed, and power. © 1982-2012 IEEE.

关键词： System-on-chip

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SSGCNet: A Sparse Spectra Graph Convolutional Network for Epileptic EEG Signal Classification

arXiv

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arXiv 2022年

作者： Wang, Jialin Gao, Rui Zheng, Haotian Zhu, Hao Shi, C.-J. Richard State Key Laboratory of ASIC and Systems The Institute of Brain-Inspired Circuits and Systems Zhangjiang Fudan International Innovation Center Fudan University Shanghai 201203 China Department of Electrical Engineering and Automation Aalto University Espoo02150 Finland Department of Electrical and Computer Engineering University of Washington SeattleWA98195 United States

In this article, we propose a sparse spectra graph convolutional network (SSGCNet) for solving Epileptic EEG signal classification problems. The aim is to achieve a lightweight deep learning model without losing model classification accuracy. We propose a weighted neighborhood field graph (WNFG) to represent EEG signals, which reduces the redundant edges between graph nodes. WNFG has lower time complexity and memory usage than the conventional solutions. Using the graph representation, the sequential graph convolutional network is based on a combination of sparse weight pruning technique and the alternating direction method of multipliers (ADMM). Our approach can reduce computation complexity without effect on classification accuracy. We also present convergence results for the proposed approach. The performance of the approach is illustrated in public and clinical-real datasets. Compared with the existing literature, our WNFG of EEG signals achieves up to 10 times of redundant edge reduction, and our approach achieves up to 97 times of model pruning without loss of classification accuracy. © 2022, CC0.

关键词： Convolutional neural networks

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Broadband and repetition rate tunable frequency comb based on electro-optic time lens with AlGaAsOI waveguide

Broadband and repetition rate tunable frequency comb based o...

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49th European Conference on Optical Communications (ECOC 2023)

作者： C. Ma C. Wang Y. Pi L. Wang Z. He J. E. Bowers L. Chang Z. Cao S. Yu Research Center of Circuits and Systems Peng Cheng Laboratory Shenzhen 518055 Guangdong People's Republic of China Department of Electrical and Computer Engineering University of California Santa Barbara CA 93106 USA State Key Laboratory of Advanced Optical Communications System and Networks Peking University Beijing 100871 People's Republic of China

We present a tunable repetition rate frequency comb realized by cascaded electro-optical modulators with a high nonlinear AlGaAs-on-isolator waveguide. 18-26.5 GHz comb spacing tunability with broadband spectra was achieved. All the devices can be integrated onto a single chip, which makes this work useful for many applications.

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Validating a Chaos Based PRBG Under Different Chaotic Maps

Validating a Chaos Based PRBG Under Different Chaotic Maps

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Panhellenic Conference on Electronics and Telecommunications (PACET)

作者： Lazaros Moysis Marcin Lawnik Christos Volos Murilo S. Baptista George F. Fragulis Sotirios K. Goudos Department of Electrical and Computer Engineering University of Western Macedonia Kozani Greece Physics Department Laboratory of Nonlinear Systems - Circuits & Complexity Aristotle University of Thessaloniki Thessaloniki Greece Department of Mechanical Engineering University of Western Macedonia Kozani Greece Department of Mathematics Applications and Methods for Artificial Intelligence Faculty of Applied Mathematics Silesian University of Technology Gliwice Poland Department of Physics Institute for Complex Systems and Mathematical Biology SUPA University of Aberdeen Aberdeen UK Physics Department ELEDIA@AUTH Aristotle University of Thessaloniki Thessaloniki Greece

Chaos-based random bit generators are abundantly used in chaos-based encryption and security applications, as a fast, deterministic source of randomness, to perform actions like permutation and substitution. The chaotic map used as a source of randomness though may heavily affect the bit generator’s statistical randomness, key space, and speed. Thus, any given bit generator may not be equally efficient for all the chaotic maps used as a seed. Motivated by this, the present work considers a bit generator that utilizes a common modulo-based hashing technique, and studies its performance under a plethora of different chaotic maps. For each map, the generator is evaluated with respect to randomness, key space, and operations per bit ratio. This analysis can serve as a guideline for random bit generator usage in future chaos-based encryption designs.

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ReBoc: Accelerating Block-Circulant Neural Networks in ReRAM

ReBoc: Accelerating Block-Circulant Neural Networks in ReRAM

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2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020

作者： Wang, Yitu Chen, Fan Song, Linghao Richard Shi, C.-J. Li, Hai Helen Chen, Yiran State Key Laboratory of ASIC and Systems Fudan University Shanghai China Institution of Brain-inspired Circuits and Systems Fudan University Shanghai China Department of Electrical and Computer Engineering Duke University DurhamNC United States Department of Electrical and Computer Engineering University of Washington SeattleWA United States

ISBN: (纸本)9783981926347

Deep neural networks (DNNs) emerge as a key component in various applications. However, the ever-growing DNN size hinders efficient processing on hardware. To tackle this problem, on the algorithmic side, compressed DNN models are explored, of which block-circulant DNN models are memory efficient and hardware-friendly;on the hardware side, resistive random-access memory (ReRAM) based accelerators are promising for in-situ processing of DNNs. In this work, we design an accelerator named ReBoc for accelerating block-circulant DNNs in ReRAM to reap the benefits of light-weight models and efficient in-situ processing simultaneously. We propose a novel mapping scheme which utilizes Horizontal Weight Slicing and Intra-Crossbar Weight Duplication to map block-circulant DNN models onto ReRAM crossbars with significant improved crossbar utilization. Moreover, two specific techniques, namely Input Slice Reusing and Input Tile Sharing are introduced to take advantage of the circulant calculation feature in block- circulant DNNs to reduce data access and buffer size. In REBOC, a DNN model is executed within an intra-layer processing pipeline and achieves respectively 96× and 8.86× power efficiency improvement compared to the state-of-the-art FPGA and ASIC accelerators for block-circulant neural networks. Compared to ReRAM-based DNN accelerators, REBOC achieves averagely 4.1× speedup and 2.6× energy reduction. © 2020 EDAA.

关键词： Deep neural networks

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Stretchable triboelectric sensor for measurement of the forearm muscles movements and fingers motion for Parkinson's disease assessment and assisting technologies

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Medical Devices and Sensors 2021年第1期4卷

作者： Vera Anaya, David Yuce, Mehmet Rasit Department of Electrical and Computer Systems Engineering Monash University ClaytonVIC Australia Biomedical Integrated Circuits and Sensors Laboratory Monash University ClaytonVIC Australia

Parkinson's disease (PD) is a degenerative, neurological disease that causes motor dysfunctions on the patient. Currently, the symptoms and progression of the disease are assessed by physicians who diagnose through careful observation, according to the Movement Disorder Society (MDS)-sponsored Revision of the Unified Parkinson's Disease Rating Scale (UPDRS). In this manuscript, we report a portable sensor device based on a flexible Triboelectric Nanogenerator (TENG) formed from a dielectric material with a size of 4 cm × 3.5 cm and an aluminium (Al) electrode with dimensions of 2 mm × 3 mm, to monitor the movement of forearm muscles and tendons. When the hand or fingers extend or flex, the short gap between the dielectric polymer and the small conductor changes, generating a voltage due to triboelectric contact. The device is used to assess localized bradykinesia and rigidity of fingers and hands, as well as wrist and arm tremors. The voltage signal of the proposed sensor shows different waveform shapes, time duration and amplitude for each level of classification from ‘normal’ to ‘moderate’ status, described on the MDS-UPDRS examination of hand movement, finger tapping and pronation–supination movement. Hence, we demonstrated that the proposed sensor can potentially be used for quantification of the symptoms and diagnosing. In addition, single finger motion tracking is also achieved by placing the triboelectric sensor in different positions around the forearm, close to the tendon connected to the finger under test. This way we avoid the placement of the sensor directly on the fingers, improving comfortability and long-term wearability. The presented TENG sensor is fully integrated with the processing and the transmission board exploring new opportunities for triboelectric transducers in small motion detection of muscles. The future aim of this research is to provide real-time monitoring of the disease progression as feedback for personalized treatment of the PD pat

关键词： Nanogenerators

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The Challenges of Music Deep Learning for Traditional Music

The Challenges of Music Deep Learning for Traditional Music

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International Conference on Modern circuits and systems Technologies (MOCAST)

作者： Lazaros Moysis Lazaros Alexios Iliadis Sotirios P. Sotiroudis Kostas Kokkinidis Panagiotis Sarigiannidis Spiridon Nikolaidis Christos Volos Achilles D. Boursianis Dimitrios Babas Maria S. Papadopoulou Sotirios K. Goudos Laboratory of Nonlinear Systems - Circuits & Complexity School of Physics Aristotle University of Thessaloniki Thessaloniki Greece Department of Mechanical Engineering University of Western Macedonia Kozani Greece ELEDIA@AUTH School of Physics Aristotle University of Thessaloniki Thessaloniki Greece Department of Applied Informatics University of Macedonia Thessaloniki Greece Department of Electrical and Computer Engineering University of Western Macedonia Kozani Greece School of Physics Aristotle University of Thessaloniki Thessaloniki Greece Department of Information and Electronic Engineering International Hellenic University Sindos Greece

Numerous applications for music listeners, educators, DJs, and musicians have been created over the past decade as the field of Music Deep Learning has expanded. Evidently, the majority of works rely on training their architectures using well-established databases, which consist primarily of Western popular music genres. This creates a deficiency in applications focusing on traditional and regional music, which are vital to preserving culture. As an increasing number of research groups begin to develop works centered on traditional music, several practical challenges for applying deep learning arise. This work discusses these issues and the future of deep learning in the study of traditional music.

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Resistive Memory-based Neural Differential Equation Solver for Score-based Diffusion Model

arXiv

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arXiv 2024年

作者： Yang, Jichang Chen, Hegan Chen, Jia Wang, Songqi Wang, Shaocong Yu, Yifei Chen, Xi Wang, Bo Zhang, Xinyuan Cui, Binbin Li, Yi Lin, Ning Xu, Meng Li, Yi Xu, Xiaoxin Qi, Xiaojuan Wang, Zhongrui Zhang, Xumeng Shang, Dashan Wang, Han Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering the University of Hong Kong Hong Kong ACCESS – AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai200433 China Institute of the Mind the University of Hong Kong Hong Kong University of Chinese Academy of Sciences Beijing100049 China School of Integrated Circuits Hubei Key Laboratory for Advanced Memories Huazhong University of Science and Technology Wuhan430074 China Department of Electronic and Computer Engineering the Hong Kong University of Science and Technology Hong Kong

Human brains image complicated scenes when reading a novel. Replicating this imagination is one of the ultimate goals of AI-Generated Content (AIGC). However, current AIGC methods, such as score-based diffusion, are still deficient in terms of rapidity and efficiency. This deficiency is rooted in the difference between the brain and digital computers. Digital computers have physically separated storage and processing units, resulting in frequent data transfers during iterative calculations, incurring large time and energy overheads. This issue is further intensified by the conversion of inherently continuous and analog generation dynamics, which can be formulated by neural differential equations, into discrete and digital operations. Inspired by the brain, we propose a time-continuous and analog in-memory neural differential equation solver for score-based diffusion, employing emerging resistive memory. The integration of storage and computation within resistive memory synapses surmount the von Neumann bottleneck, benefiting the generative speed and energy efficiency. The closed-loop feedback integrator is time-continuous, analog, and compact, physically implementing an infinite-depth neural network. Moreover, the software-hardware co-design is intrinsically robust to analog noise. We experimentally validate our solution with 180 nm resistive memory in-memory computing macros. Demonstrating equivalent generative quality to the software baseline, our system achieved remarkable enhancements in generative speed for both unconditional and conditional generation tasks, by factors of 64.8 and 156.5, respectively. Moreover, it accomplished reductions in energy consumption by factors of 5.2 and 4.1. Our approach heralds a new horizon for hardware solutions in edge computing for generative AI applications. © 2024, CC BY-NC-SA.

关键词： Diffusion

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Continuous-Time Digital Twin with Analogue Memristive Neural Ordinary Differential Equation Solver

arXiv

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arXiv 2024年

作者： Chen, Hegan Yang, Jichang Chen, Jia Wang, Songqi Wang, Shaocong Wang, Dingchen Tian, Xinyu Yu, Yifei Chen, Xi Lin, Yinan He, Yangu Wu, Xiaoshan Li, Yi Zhang, Xinyuan Lin, Ning Xu, Meng Li, Yi Zhang, Xumeng Wang, Zhongrui Wang, Han Shang, Dashan Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong ACCESS – AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong Institute of the Mind The University of Hong Kong Hong Kong Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China University of Chinese Academy of Sciences Beijing100049 China School of Integrated Circuits Hubei Key Laboratory for Advanced Memories Huazhong University of Science and Technology Wuhan430074 China State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai200433 China Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Hong Kong

Digital twins, the cornerstone of Industry 4.0, replicate real-world entities through computer models, revolutionising fields such as manufacturing management and industrial automation. Recent advances in machine learning provide data-driven methods for developing digital twins using discrete-time data and finite-depth models on digital computers. However, this approach fails to capture the underlying continuous dynamics and struggles with modelling complex system behaviour. Additionally, the architecture of digital computers, with separate storage and processing units, necessitates frequent data transfers and Analogue-Digital (A/D) conversion, thereby significantly increasing both time and energy costs. Here, we introduce a memristive neural ordinary differential equation (ODE) solver for digital twins, which is capable of capturing continuous-time dynamics and facilitates the modelling of complex systems using an infinite-depth model. By integrating storage and computation within analogue memristor arrays, we circumvent the von Neumann bottleneck, thus enhancing both speed and energy efficiency. We experimentally validate our approach by developing a digital twin of the HP memristor, which accurately extrapolates its nonlinear dynamics, achieving a 4.2-fold projected speedup and a 41.4-fold projected decrease in energy consumption compared to state-of-the-art digital hardware, while maintaining an acceptable error margin. Additionally, we demonstrate scalability through experimentally grounded simulations of Lorenz96 dynamics, exhibiting projected performance improvements of 12.6-fold in speed and 189.7-fold in energy efficiency relative to traditional digital approaches. By harnessing the capabilities of fully analogue computing, our breakthrough accelerates the development of digital twins, offering an efficient and rapid solution to meet the demands of Industry 4.0. © 2024, CC BY-NC-SA.

关键词： Energy utilization

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