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arXiv 2024年

作者： Zhang, Yue Zhang, Woyu Wang, Shaocong Lin, Ning Yu, Yifei He, Yangu Wang, Bo Jiang, Hao Lin, Peng Xu, Xiaoxin Qi, Xiaojuan Wang, Zhongrui Zhang, Xumeng Shang, Dashan Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100049 China ACCESS – AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong Institute of the Mind The University of Hong Kong Hong Kong Key Lab of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing100049 China State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai200433 China University of Chinese Academy of Sciences Beijing100049 China College of Computer Science and Technology Zhejiang University Zhejiang310027 China Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Hong Kong

The brain is dynamic, associative and efficient. It reconfigures by associating the inputs with past experiences, with fused memory and processing. In contrast, AI models are static, unable to associate inputs with past experiences, and run on digital computers with physically separated memory and processing. We propose a hardware-software co-design, a semantic memory-based dynamic neural network (DNN) using memristor. The network associates incoming data with the past experience stored as semantic vectors. The network and the semantic memory are physically implemented on noise-robust ternary memristor-based Computing-In-Memory (CIM) and Content-Addressable Memory (CAM) circuits, respectively. We validate our co-designs, using a 40nm memristor macro, on ResNet and PointNet++ for classifying images and 3D points from the MNIST and ModelNet datasets, which not only achieves accuracy on par with software but also a 48.1% and 15.9% reduction in computational budget. Moreover, it delivers a 77.6% and 93.3% reduction in energy consumption. © 2024, CC BY.

关键词： Memristors

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A DC-Ka-Band 7-Bit Passive Attenuator with Capacitive-Compensation-Based Bandwidth Extension Technique in 55-nm CMOS

A DC-Ka-Band 7-Bit Passive Attenuator with Capacitive-Compen...

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作者： Zhang, Zijiang Li, Nayu Gao, Huiyan Li, Min Wang, Shaogang Kuan, Yen-Cheng Song, Chunyi Yu, Xiaopeng Gu, Qun Jane Xu, Zhiwei Ocean College Institute of Marine Electronics and Intelligent Systems Zhejiang University Zhoushan China College of Information Science and Electronic Engineering Institute of VLSI Design Zhejiang University Hangzhou China Department of Electrical and Computer Engineering University of California at Davis DavisCA United States Engineering Research Center of Oceanic Sensing Technology and Equipment Ministry of Education Zhoushan316021 China Key Laboratory of Ocean Observation-Imaging Testbed of Zhejiang Province Zhoushan316021 China International College of Semiconductor Technology National Chiao Tung University Hsinchu30010 Taiwan

This article presents a 7-bit wideband passive attenuator with low insertion loss (IL) and high attenuation accuracy in 55-nm CMOS technology. The $\pi $ -type and bridge-T-type attenuation units utilize an effective capacitive compensation technique, whose bandwidth extension mechanism is detailed in a single-unit pole-zero analysis. The matching-induced performance deterioration is investigated to minimize amplitude and phase errors at the chip level. The fabricated attenuator demonstrates a 32.4-dB attenuation range with a 0.255-dB resolution and a 3.5-8.4-dB IL from dc to 32 GHz. The measured root-mean-square (rms) amplitude and phase errors are below 0.32 dB and 5.33°, respectively. The attenuator occupies a 0.054-mm2 core area and consumes negligible power. © 1963-2012 IEEE.

关键词： Insertion losses

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Time-varying Algorithm for Swarm Robotics

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IEEE/CAA Journal of Automatica Sinica 2018年第1期5卷 217-222页

作者： Ligang Hou Fangwen Fan Jingyan Fu Jinhui Wang Laboratory of VLSI and Systems College of Microelectronics Beijing University of Technology Department of Electrical and Computer Engineering North Dakota State University

Ever since the concept of swarm intelligence was brought out, a variety of control algorithms for swarm robotics has been put forward, and many of these algorithms are stable enough and efficient. Most of the researches only take an invariable controller which functions through the whole stage into consideration, the situation in which controller changes over time is rarely taken into account. However, there are limitations for invariable controller dominated algorithms in practical situation,which makes them unable to meet changing environment. On the contrary, variable controller is more flexible and can be able to adapt to complex environment. Considering such advantages,a time-varying algorithm for swarm robotics is presented in this paper. The algorithm takes time as one of the independent variables so that the controller is no longer fixed through the time,but can be changed over time, which brings more choices for the swarm robot system. In this paper, some relevant simulations are designed to test the algorithm. Different control strategies are applied on the same flock during the time, and a more complex,flexible and practical control effect is acquired successfully.

关键词： Advanced self-organization behavior agentbased distributed control system aggregation swarm intelligence

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Efficient and accurate neural field reconstruction using resistive memory

arXiv

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arXiv 2024年

作者： Yu, Yifei Wang, Shaocong Zhang, Woyu Zhang, Xinyuan Wu, Xiuzhe He, Yangu Yang, Jichang Zhang, Yue Lin, Ning Wang, Bo Chen, Xi Wang, Songqi Zhang, Xumeng Qi, Xiaojuan Wang, Zhongrui Shang, Dashan Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong Hong Kong ACCESS – AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong Hong Kong Institute of Mind The University of Hong Kong Hong Kong Hong Kong Key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China University of Chinese Academy of Sciences Beijing100049 China Frontier Institute of Chip and System Fudan University Shanghai200433 China Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Hong Kong Hong Kong

Human beings construct perception of space by integrating sparse observations into massively interconnected synapses and neurons, offering a superior parallelism and efficiency. Replicating this capability in AI finds wide applications in medical imaging, AR/VR, and embodied AI, where input data is often sparse and computing resources are limited. However, traditional signal reconstruction methods on digital computers face both software and hardware challenges. On the software front, difficulties arise from storage inefficiencies in conventional explicit signal representation. Hardware obstacles include the von Neumann bottleneck, which limits data transfer between the CPU and memory, and the limitations of CMOS circuits in supporting parallel processing. We propose a systematic approach with software-hardware co-optimizations for signal reconstruction from sparse inputs. Software-wise, we employ neural field to implicitly represent signals via neural networks, which is further compressed using low-rank decomposition and structured pruning. Hardware-wise, we design a resistive memory-based computing-in-memory (CIM) platform, featuring a Gaussian Encoder (GE) and an MLP Processing Engine (PE). The GE harnesses the intrinsic stochasticity of resistive memory for efficient input encoding, while the PE achieves precise weight mapping through a Hardware-Aware Quantization (HAQ) circuit. We demonstrate the system’s efficacy on a 40nm 256Kb resistive memory-based in-memory computing macro, achieving 31.5×, 35.5×, and 47.2× energy efficiency improvements and 10.8×, 38.8×, and 6.2× parallelism improvements without compromising reconstruction quality in tasks like 3D CT sparse reconstruction, novel view synthesis, and novel view synthesis for dynamic scenes. This work advances the AI-driven signal restoration technology and paves the way for future efficient and robust medical AI and 3D vision applications. Copyright © 2024, The Authors. All rights reserved.

关键词： Signal reconstruction

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Pruning random resistive memory for optimizing analogue AI

arXiv

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arXiv 2023年

作者： Li, Yi Wang, Songqi Zhao, Yaping Wang, Shaocong Zhang, Woyu He, Yangu Lin, Ning Cui, Binbin Chen, Xi Zhang, Shiming Jiang, Hao Lin, Peng Zhang, Xumeng Qi, Xiaojuan Wang, Zhongrui Xu, Xiaoxin Shang, Dashan Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China ACCESS – AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong State Key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Frontier Institute of Chip and System Fudan University Shanghai200433 China College of Computer Science and Technology Zhejiang University Zhejiang310027 China Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Hong Kong University of Chinese Academy of Sciences Beijing100049 China Institute of Mind The University of Hong Kong Hong Kong

The rapid advancement of artificial intelligence (AI) has been marked by the large language models exhibiting human-like intelligence. However, these models also present unprecedented challenges to energy consumption and environmental sustainability, which are exacerbated by the increasing number of users and the development of even larger models. One promising solution is to revisit analogue computing, a technique that predates digital computing and exploits emerging analogue electronic devices, such as resistive memory, which features in-memory computing, high scalability, and nonvolatility that addresses the von Neumann bottleneck, slowdown of Moore’s law, and volatile DRAM of conventional digital hardware. However, analogue computing still faces the same challenges as before: programming nonidealities and expensive programming due to the underlying devices physics. Therefore, leveraging the efficiency advantage while mitigating the programming disadvantage of analogue computing with resistive memory is a major open problem in AI hardware and electronics communities. Here, we report a universal solution, software-hardware co-design using structural plasticity-inspired edge pruning to optimize the topology of a randomly weighted analogue resistive memory neural network. Software-wise, the topology of a randomly weighted neural network is optimized by pruning connections rather than precisely tuning resistive memory weights. Hardware-wise, we reveal the physical origin of the programming stochasticity using transmission electron microscopy, which is leveraged for large-scale and low-cost implementation of an overparameterized random neural network containing high-performance sub-networks. We implemented the co-design on a 40nm 256K resistive memory macro, observing 17.3% and 19.9% accuracy improvements in image and audio classification on FashionMNIST and Spoken digits datasets, as well as 9.8% (2%) improvement in PR (ROC) in image segmentation on DRIVE datasets, r

关键词： Energy utilization

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ON-OFF Neuromorphic ISING Machines using Fowler-Nordheim Annealers

arXiv

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arXiv 2024年

作者： Chen, Zihao Xiao, Zhili Akl, Mahmoud Leugring, Johannes Olajide, Omowuyi Malik, Adil Dennler, Nik Harper, Chad Bose, Subhankar Gonzalez, Hector A. Eshraghian, Jason Pignari, Riccardo Urgese, Gianvito Andreou, Andreas G. Shankar, Sadasivan Mayr, Christian Cauwenberghs, Gert Chakrabartty, Shantanu Department of Electrical and Systems Engineering Washington University in St. Louis One Brookings Drive St. LouisMO63130 United States Department of Bioengineering University of California 9500 Gilman Dr La Jolla San DiegoCA92093 United States SpiNNcloud Systems GmbH Freibergerstr. 37 Dresden01067 Germany Department of Electrical and computer engineering Johns Hopkins University 3400 N. Charles Street BaltimoreMD21218 United States SLAC National Accelerator Laboratory 2575 Sand Hill Road Menlo ParkCA94025 United States Department of Electrical and Electronic Engineering Imperial College London Exhibition Rd LondonSW7 2AZ United Kingdom International Centre for Neuromorphic Engineering Western Sydney University Penrith Second Ave KingswoodNSW2747 Australia Department of Physics University of California Berkeley University Avenue and Oxford St BerkeleyCA94720 United States Department of Electrical and Computer Engineering University of California Santa Cruz 1156 High Street Santa CruzCA95064 United States Politecnico di Torino Address: Corso Duca degli Abruzzi 24 Torino10129 Italy Redwood Center for Theoretical Neuroscience Helen Wills Neuroscience Institute University of California Berkeley University Avenue and Oxford St BerkeleyCA94720 United States Biocomputation Group University of Hertfordshire Exhibition Rd LondonSW7 2AZ United Kingdom Materials Science and Engineering Stanford University 450 Jane Stanford Way StanfordCA94305 United States Highly-Parallel VLSI-Systems and Neuro-Microelectronics Technische Universität Dresden Mommsenstraße 12 Dresden01069 Germany Scads.AI: Center for scalable data analytics and artificial intelligence Strehlener Street 12 14 Dresden01069 Germany

We introduce NeuroSA, a neuromorphic architecture specifically designed to ensure asymptotic convergence to the ground state of an Ising problem using an annealing process that is governed by the physics of quantum mechanical tunneling using Fowler-Nordheim (FN). The core component of NeuroSA consists of a pair of asynchronous ON-OFF neurons, which effectively map classical simulated annealing (SA) dynamics onto a network of integrate-and-fire (IF) neurons. The threshold of each ON-OFF neuron pair is adaptively adjusted by an FN annealer which replicates the optimal escape mechanism and convergence of SA, particularly at low temperatures. To validate the effectiveness of our neuromorphic Ising machine, we systematically solved various benchmark MAX-CUT combinatorial optimization problems. Across multiple runs, NeuroSA consistently generates solutions that approach the state-of-the-art level with high accuracy (greater than 99%), and without any graph-specific hyperparameter tuning. For practical illustration, we present results from an implementation of NeuroSA on the SpiNNaker2 platform, highlighting the feasibility of mapping our proposed architecture onto a standard neuromorphic accelerator platform. © 2024, CC BY-NC-SA.

关键词： Simulated annealing

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A 2.0-2.9 GHz Digital Ring-Based Injection-Locked Clock Multiplier Using a Self-Alignment Frequency Tracking Loop for Reference Spur Reduction

A 2.0-2.9 GHz Digital Ring-Based Injection-Locked Clock Mult...

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IEEE Symposium on Radio Frequency Integrated circuits (RFIC)

作者： Rongjin Xu Dawei Ye Liangjian Lyu C.-J. Richard Shi State Key Laboratory of ASIC and System Fudan University China Institute of Brain-inspired Circuits and Systems (iBiCAS) Fudan University China Department of Electrical and Computer Engineering University of Washington Seattle USA

ISBN: (数字)9781728168098

ISBN: (纸本)9781728168104

This paper presents a 2.0-2.9 GHz digital ring-based injection-locked clock multiplier (ILCM) in a 65 nm CMOS process. A self-alignment frequency tracking loop (SA-FTL) with background delay calibration is proposed to improve the accuracy of injection timing. Since the frequency mismatch of the free-running oscillator and the target frequency is minimized without delay error, the reference spur is reduced to -55.6 dBc, exhibiting 15.9 dB improvement comparing to the case that the SA-FTL is off. The proposed ILCM achieves 545 fs RMS jitter at 2.5 GHz output frequency with a power consumption of 3.1 mW, achieving the FoM of 240.3 dB.

关键词： Delays Clocks Oscillators Jitter Calibration Tracking loops

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A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification

A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time...

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IEEE International Symposium on circuits and systems (ISCAS)

作者： Yuting Tu Rongjin Xu Dawei Ye Liangjian Lyu C.-J. Richard Shi State Key Laboratory of ASIC and System Fudan University Shanghai 201203 China Institute of Brain-inspired Circuits and Systems (iBiCAS) Fudan University Shanghai 201203 China Department of Electrical and Computer Engineering University of Washington Seattle 98195 USA

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

This work proposes a high-speed pipelined-two-step time-to-digital converter (TDC) with a dynamic time amplification (DTA) to improve the resolution at low power. The key element of this TDC is the DTA. It samples the residual time errors as voltages held in the MOM capacitors and discharges them to generate the amplified time difference. Thanks to the dynamic time-voltage-time conversion, the DTA realizes high linearity and power efficiency, and can be employed to build a pipeline TDC architecture with high sampling frequency because of its sample and hold operation. Moreover, the DTA maintains constant gain, so only a one-time forground calibration for gain mismatch is required in this TDC. Simulations show that the TDC designed in 65 nm CMOS achieves 8-bit, 1.75 ps of time resolution, and 1 LSB INL and 1.6 LSB DNL with one-time foreground calibration at 400 MHz sampling frequency while just consuming 726 μW power, which corresponds to 18.45 fJ/Conv. FoM.

关键词： Delays Calibration Inverters Capacitors Linearity Tin

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Erratum to “A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain” [Nov 21 3360-3374]

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IEEE Journal of Solid-State circuits 2022年第2期57卷 671-671页

作者： Dawei Ye Rongjin Xu C.-J. Richard Shi State Key Laboratory of ASIC and System Fudan University Shanghai China Institute of Brain-Inspired Circuits and Systems (iBiCAS) Fudan University Shanghai China MOE Frontiers Center for Brain Science Fudan University Shanghai China Department of Electrical and Computer Engineering University of Washington Seattle WA USA

In the above article [1] , Fig. 4 is wrong. The correct one is shown below:

关键词： Interference suppression Internet of Things CMOS analog integrated circuits Low-noise amplifiers

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An HMM-based averaging approach for creating mean motion data from a full-body Motion Capture system to support the development of a biomechanical model: Sensor-assisted functionalization of furniture in the hospital and care sector

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Current Directions in Biomedical engineering 2018年第1期4卷 1-5页

作者： Kitzig, Andreas Demmer, Julia Bolten, Tobias Naroska, Edwin Stockmanns, Gudrun Viga, Reinhard Grabmaier, Anton Niederrhein University of Applied Sciences Faculty of Electrical Engineering and Computer Science Ambient Intelligence Laboratory Reinarzstr. 49 Krefeld 47805 Germany University of Duisburg Essen Department of Electronic Components and Circuits Bismarkstr. 81 Duisburg 47057 Germany Fraunhofer Institute for Microelectronic Circuits and Systems (IMS) Finkenstraße 61 Duisburg 47057 Germany

Motion capture systems or MoCap systems are used for game development and in the field of sports for the assessment and digitalization of human movement. Furthermore, MoCap systems are also used in the medical and therapeutic field for the analysis of human movement patterns. As examples gait analysis or examination of the musculoskeletal system and its function should be mentioned. Most application relate to a specific person and their movement or to the comparison of movements of different people. Within the scope of this paper an averaged motion sequence is supposed to be generated from MoCap data in order to be able to use it in the field of biomechanical modeling and simulation. For the averaging of individual movement sequences of different persons a Hidden Markov Model (HMM) based approach is presented. © 2018 author name(s).

关键词： Hidden Markov models

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