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检索条件"机构=Electrical and Computer Engineering Department VLSI Circuits and Systems Laboratory"

共 143 条记录，以下是61-70 订阅

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3D computational modeling of epiretinal prosthesis stimulation of the ganglion cell

3D computational modeling of epiretinal prosthesis stimulati...

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IEEE EMBS International Conference on Information Technology Applications in Biomedicine (ITAB)

作者： Shabnam Novin Hamid Abrishami Moghaddam Amir Masoud Sodagar Amin Mahnam Research Laboratory for Integrated Circuits and Systems (I CAS) Department of Electrical and Computer Engineering K.N. Toosi University of Technology Tehran Iran Research Laboratory for Machine Vision and Medical Image Processing (MVMIP) Department of Electrical and Computer Engineering K.N. Toosi University of Technology Tehran Iran Ecole Polytechnique de Montreal Montreal QUE Canada Department of Biomedical Engineering School of Engineering University of Isfahan Isfahan Iran

Here we present a modeling for electrical stimulation of retinal ganglion cell. This modeling can be used in epiretinal prosthesis to come up with proper electrical stimulation parameters. The model that we present is a novel one based on the anatomy of the cell. The excitation process of the electrically stimulated retinal cells is simulated in a two step procedure. In the first step the ganglion target cell is represented considering all of its compartments and in a second step the extracellular potential along the neural structure is calculated and finally the membrane voltage response to the applied stimulations is analyzed. A monopolar point electrode was positioned above the cell in an infinite and homogenous environment and the monophasic and biphasic pulses were used as stimulating current. The results show that the responses are in accordance with the values and diagrams of experimental results more than the previous models.

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A 64-Channel Neural Signal Processor/Compressor Based on Haar Wavelet Transform

A 64-Channel Neural Signal Processor/Compressor Based on Haa...

引用

Annual International Conference of the IEEE engineering in Medicine and Biology Society

作者： Mohammad Ali Shaeri Amir M. Sodagar Hamid Abrishami-Moghaddam Research Laboratory for Integrated Circuits and Systems (ICAS) Department of Electrical and Computer Engineering K.N. Toosi University of Technology Department of Electrical and Computer Engineering K.N. Toosi University of Technology

ISBN: (纸本)9781424441211

A signal processor/compressor dedicated to implantable neural recording microsystems is presented. Signal compression is performed based on Haar wavelet. It is shown in this paper that, compared to other mathematical transforms already used for this purpose, compression of neural signals using this type of wavelet transform can be of almost the same quality, while demanding less circuit complexity and smaller silicon area. Designed in a 0.13-μm standard CMOS process, the 64-channel 8-bit signal processor reported in this paper occupies 113μm×110μm of silicon area. It operates under a 1.8-V supply voltage at a master clock frequency of 3.2MHz.

关键词： wavelet transforms signal compression circuit complexity supply voltage signal processor reference clock paper 8-bit Silicon Microelectromechanical devices

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Design of Double Layer Printed Spiral Coils for Wirelessly-Powered Biomedical Implants

Design of Double Layer Printed Spiral Coils for Wirelessly-P...

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Annual International Conference of the IEEE engineering in Medicine and Biology Society

作者： Ehsan Ashoori Farzad Asgarian Amir M. Sodagar Euisik Yoon Research Laboratory for Integrated Circuits and Systems (ICAS) Electrical & Computer Eng. Dept K.N. Toosi University of Technology Research Laboratory for Integrated Circuits and Systems (ICAS) Electrical & Computer Eng. Dept. K.N. Toosi University of Technology Center for Wireless Integrated Microsystems Department of Electrical Engineering and Computer Science University of Michigan

ISBN: (纸本)9781424441211

In this paper employing double layer printed spiral coils (PSCs) is proposed for wireless power transmission in implantable biomedical applications. Detailed modeling of this type of PSCs is presented. Both calculations and measurements of fabricated double layer PSCs indicate that this structure can decrease the size of typical single layer PSCs without any change in the most important parameters of the coils, such as quality factor. Also, it is shown that with equal PSC dimensions and design parameters, double layer PSCs achieve significantly higher inductances and quality factors. Ultimately, a pair of double layer PSCs with a distance of 5 mm in air is used in an inductive link. The power transfer efficiency of this link is about 79.8% with a carrier frequency of 5 MHz and coupling coefficient of 0.189.

关键词： Double layer helical coil Quality factor TRANSFER EFFICIENCY Implants and Prostheses CARRIER FREQUENCY biomedical

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IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs

IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Base...

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International Conference on Field Programmable Logic and Applications

作者： Zhe Feng Naifeng Jing GengSheng Chen Yu Hu Lei He Electrical Engineering Department University of California Los Angeles USA School of Microelectronics Shanghai Jiao Tong University China State Key Laboratory of Application Specific Circuits and Systems Fudan University Shanghai China Electrical and Computer Engineering Department University of Alberta Canada

SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to Single Event Upsets (SEUs). We show that a large portion (40%-60% for the circuits in our experiments) of the total used LUT configuration bits are don't care bits, and propose to decide the logic values of don't care bits such that soft errors are reduced. Our approaches are efficient and do not change LUT level placement and routing. Therefore, they are suitable for design closure. For the ten largest combinational MCNC benchmark circuits mapped for 6-LUTs, our approaches obtain 20% chip level Mean Time To Failure (MTTF) improvements, compared to the baseline mapped by Berkeley ABC mapper. They obtain 3× more chip level MTTF improvements and are 128× faster when compared to the existing best in-place IPD algorithm.

关键词： Table lookup Field programmable gate arrays Integrated circuit interconnections Integrated circuit reliability Observability Helium

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A special-purpose embedded controller for an implantable spinal cord stimulation system

A special-purpose embedded controller for an implantable spi...

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Iranian Conference of Biomedical engineering (ICBME)

作者： Hajar Nikbakht Amir M. Sodagar Mahmood Seifouri Saeid Barati Research Laboratory for Integrated Circuits and Systems (ICAS) Faculty of ECE K. N. Toosi University of Technology Tehran Iran Electrical and Computer Engineering Department Shahid Rajaee Teacher Training University Tehran Iran Ecole Polytechnique de Montreal Montreal QUE Canada Electrical and Computer Engineering Department Shahid Rajaee Teacher Training University Tehran Iran

This paper reports on a special-purpose controller dedicated to an implantable spinal cord electrical stimulation (SCS) microsystem. The controller supports parallel biphasic stimulation pulses on 16 channels concurrently, and recording neural response on any one of the sites with 8 bits of resolution. Anodic and cathodic pulse amplitudes are programmable with 8 bits of resolution, while the timing of the pulses is controllable in the real time through the data packets receiving serially via a wireless link.

关键词： electrical stimulation Educational institutions Synchronization Wireless communication Pain Spinal cord

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Gate Diffusion Input (GDI) logic in standard CMOS nanoscale process

Gate Diffusion Input (GDI) logic in standard CMOS nanoscale ...

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IEEE Convention of the electrical and ELectronic Engineers in Israel

作者： Arkadiy Morgenshtein Idan Shwartz Alexander Fish Low Power Circuits and Systems Laboratory (LPC&S) The VLSI Systems Center Department of Electrical and Computer Engineering Ben-Gurion University of the Negev Beersheba Israel

In this paper CMOS compatible Gate Diffusion Input (GDI) design technique is proposed. The GDI method enables the implementation of a wide range of complex logic functions using only two transistors. This method is suitable for the design of low-power logic gates, with a much smaller area than Static CMOS and existing PTL techniques. As opposite to our originally proposed GDI logic, the modified GDI logic is fully compatible for implementation in a standard CMOS process. Simulations of basic GDI gates under process and temperature corners in 40nm CMOS process are shown and compared to similar CMOS gates. We show that while having the same delay, GDI gates achieve leakage and active power reduction of up to 70% and 50%, respectively.

关键词： Logic gates CMOS integrated circuits Transistors Threshold voltage Leakage current CMOS process Semiconductor device modeling

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Designing for spectral conformity: Issues in power amplifier design

Designing for spectral conformity: Issues in power amplifier...

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International Waveform Diversity and Design Conference

作者： Baylis, Charles Wang, Loria Moldovan, Matthew Martin, Josh Miller, Hunter Cohen, Larry De Graaf, Jean Wireless and Microwave Circuits and Systems Program Department of Electrical and Computer Engineering Baylor University Waco TX 76798 United States Naval Research Laboratory Radar Division Washington DC 20375 United States

ISBN: (纸本)9781424482009

Spectral constraints placed upon radar systems by regulatory agencies require the design of highly linear amplifiers. Spectral spreading in power amplifiers is a result of transistors operated in the nonlinear regime to optimize efficiency. Several different methods are employed by power amplifier designers to maximize both linearity and efficiency. The methods of predistortion, feedforward, envelope tracking, Doherty, and "Linear Amplification Using Nonlinear Components" (LINC) are discussed in this paper. Tradeoffs and challenges inherent in these design approaches are surveyed. ©2010 IEEE.

关键词： Efficiency

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Input Vector Control efficiency in sub-micron CMOS technologies

Input Vector Control efficiency in sub-micron CMOS technolog...

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IEEE Convention of the electrical and ELectronic Engineers in Israel

作者： Dmitry Shurin Evgeniy Kvaktun Alexander Fish Low Power Circuits and Systems Laboratory (LPC&S) The VLSI Systems Center Department of Electrical and Computer Engineering Ben-Gurion University of the Negev Beersheba Israel

The efficiency of the Input Vector Control (IVC) method in sub-micron technologies is examined. The IVC is a well known method for leakage current reduction during standby mode in digital circuits. Using the IVC method, a unique combination of input signal values, also referred to as a Minimum Leakage Vector (MLV), can be found for every circuit to minimize its standby leakage currents. While the IVC method was thoroughly examined for old process nodes, its efficiency in sub-micron technologies has not been investigated. Increases in gate and sub-threshold leakages, as well as the introduction of Deep Sub-Micron (DSM) effects that accompany technology scaling, significantly affect the MLV of a digital gate. In this paper, the efficiency of IVC for basic CMOS gates was examined in 90 nm, 65 nm and 40 nm standard CMOS technologies. The impact of gate sizing on the MLV was studied at different process corners. Simulation results show that while the IVC method is still efficient for advanced technologies, a gate's MLV is less stable with respect to the gate size and process variations.

关键词： Logic gates Gate leakage Transistors CMOS integrated circuits CMOS technology Very large scale integration

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Electro-magnetic sensing and actuation array on silicon substrate platforms

Electro-magnetic sensing and actuation array on silicon subs...

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IEEE Nanotechnology Materials and Devices Conference (NMDC)

作者： Faisal T. Abu-Nimeh Fathi M. Salem Circuits Systems and Neural Networks Laboratory Department of Electrical & Computer Engineering Michigan State University East Lansing USA

Electromagnetic arrays can be precisely constructed on silicon CMOS technology as a platform for collective non-contact sensing and manipulation of magnetic or magnetized particles of micron to nano scale. Such platforms become a tool to interact with nano scale particles on the silicon substrate and enable direct interface to measurement and computing devices. This paper overviews current efforts along this direction and presents an example design of a platform for sensing and manipulating magnetized beads on its surface using standard silicon CMOS technology. The vision is that such arrays can be easily commanded in nano seconds to realize magnetic field profiles in order to steer magnetized material in the proximity of the platform. Moreover, as technology features decrease, the size of the electromagnetic coil cells in the array would also decrease to nano scale, sharpening the sensing and manipulation resolution of the platforms.

关键词： Coils Arrays CMOS integrated circuits Silicon Force Magnetic susceptibility Metals

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Ultra-high speed atomic force microscopy: Video-rate and beyond

Ultra-high speed atomic force microscopy: Video-rate and bey...

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IEEE International Symposium on circuits and systems (ISCAS)

作者： Fathi M. Salem Integrated Circuits and Systems Laboratory Department of Electrical and Computer Engineering Michigan State University East Lansing MI USA

Ultra high-speed Atomic Force Microscopy (AFM) is desirable for imaging fast dynamic processes, e.g., protein molecules motion in their aqueous or membrane environments. The paper identifies the limiting factors of present AFMs in achieving ultra high speed imaging. Specifically, the vertical control-loop bandwidth is the key limiting factor due to the low resonance (about 150 kHz) piezo-material cantilever actuator. We then propose a bandwidth solution by using integrated coil-array actuators driven by programmable oscillators and power amplifiers as an alternative to piezo-actuators in the vertical (z-direction) control loop. The slower piezo actuation, however, can still be used in the lateral slower x-y directions to achieve scanning range in the micro-meter range. This integrated circuit and system solution potentially would turn the AFM imaging system into an ultra high speed nano-scale video camera.

关键词： Atomic force microscopy Bandwidth Actuators Proteins Biomembranes Resonance Oscillators Power amplifiers High speed integrated circuits Cameras

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