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NAVAL ENGINEERS JOURNAL 1989年第5期101卷 53-58页

作者： FRINK, JG VERVEN, DM John G. Frink is an assistant group supervisor in the Fleet Systems Department of The Johns Hopkins University Applied Physics Laboratory. He received his B.S. degree in physics from Michigan State University in 1968 and the M.S. degree in computer science from the University of Maryland in 1971. Mr. Frink worked at the Naval Surface Weapons Center White Oak Laboratory on a variety of weapons systems before joining the Applied Physics Laboratory in 1978. Mr. Frink has supervised the development of a large scale battle group simulation that successfully employs the receiver selection paradigm described herein on a hardware suite composed of an extensible number of (currently 15) processors. David M. Verven is a senior electrical engineer in the Fleet Systems Department of The Johns Hopkins University Applied Physics Laboratory. He received the B.S. degree in electrical engineering from the University of Maryland College Park in 1979 and the M. S. degree in the same discipline from The Johns Hopkins University in 1984. Mr. Verven joined the Applied Physics Laboratory in 1979 and initially worked on analysis of Navy sensor systems. In 1981 he was the AN/SPS-49 test team leader for the New Threat Upgrade (NTU) combat system land-based test. In 1982 he became involved in the development of the BBWRS system. Currently he is involved in real-time computer program development for the CEP project.

This paper documents an experiment performed by The Johns Hopkins university Applied Physics Laboratory to measure the effect of inserting a data bus into a combat system. The experiment was conducted at the Aegis computer Center located at the Naval Surface Weapons Center in Dahlgren, Virginia (NSWC/DL). The purpose of the experiment was to determine whether or not the Aegis Weapon System (the core of the Aegis Combat System) could be operated with a portion of its point-to-point interelement cables replaced by a data bus. The data bus chosen for the experiment employs message broadcasting with receiver selection. A primary goal of the experiment was to minimize the amount of Aegis computer program changes required to accommodate the data bus. The results presented in this paper will show that the experiment was a success. Key certification tests were passed with no computer program changes to the tactical elements and minimal changes in the Aegis tactical executive (ATES) program (less than 110 words changed).

关键词： Data Transmission Equipment

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programMER-TRANSPARENT COORDINATION OF RECOVERING CONCURRENT PROCESSES - PHILOSOPHY AND RULES FOR EFFICIENT IMPLEMENTATION

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IEEE TRANSACTIONS ON SOFTWARE engineering 1988年第6期14卷 810-821页

作者： KIM, KH Computer Engineering Program Department of Electrical Engineering University of California CA92717

An approach to coordination of cooperating concurrent processes, each capable of error direction and recovery, is presented. Error detection, rollback, and retry in a process are specified by a well-structured language construct called recovery block. Recovery points of processes must be properly coordinated to prevent a disastrous avalanche of process rollbacks. The approach relies on an intelligent processor system (that runs processes) capable of establishing and discarding the recovery points of interacting processes in a well coordinated manner such that a process never makes two consecutive rollbacks without making a retry between the two, and every process rollback becomes a minimum-distance rollback. Following a discussion of the underlying philosophy of the author's approach, basic rules of reducing storage and time overhead in such a processor system are discussed. Examples are drawn from the systems in which processes communicate through monitors.

关键词： PROCESSOR Philosophy concurrent process RECOVERING MONITOR

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A PERSONAL-computer SOFTWARE PACKAGE FOR POWER engineering-EDUCATION

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IEEE TRANSACTIONS ON POWER SYSTEMS 1988年第4期3卷 1864-1871页

作者： GLOVER, JD Power Systems Program Department of Electrical and Computer Engineering Northeastern University Boston MA USA

The author describes a personal-computer software package recently incorporated in the power engineering program at Northeastern university. The package includes a set of computer programs which can be utilized to support classroom instruction and student design projects. The programs cover matrix operations, symmetrical components, line constant, steady-state operation of transmission lines, power flow (100 buses), symmetrical short circuits (100 buses), short circuits (100 buses), transmission-line transients, and transient stability. The computer programs, the way they are utilized, and initial student reaction are discussed. It is concluded that the availability of the power system analysis and design software package has extended classroom capabilities and enhanced student interest in power engineering courses. The reaction of students to the software has been positive, and it has allowed them to work on more difficult and realistic problems and make it an innovative tool in the learning process.< >

关键词： Microcomputers Software packages Power engineering Power system transients Power engineering computing Transmission line matrix methods Circuits Power system stability Power system analysis computing Packaging

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Modification operations in data base machines: Where are they? 88

Modification operations in data base machines: Where are the...

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16th ACM Annual Conference on computer Science, CSC 1988

作者： Hurson, A.R. Miller, L.L. Department of Electrical Engineering Computer Engineering Program Pennsylvania State University University ParkPA16802 United States Department of Computer Science Iowa State University AmesIA50011 United States

ISBN: (纸本)0897912608

Advances in technology coupled with the inefficiency of the conventional von-Neumann type architecture in handling database systems have motivated the design and implementation of the so called database machines. Unfortunately, a majority of the proposed database machines have neglected to address proper procedures for modification operations. This negligence is partially due to the complexity of the operations and low performance of the database architectures in handling modification operations. First, the implementation of the modification operations in some database machines is overviewed. Second, we will address the mechanisms in which the relational database machine ASLM handles the modification operations. Finally, our approach is compared against the other proposed approaches in the literature. © 1988 ACM.

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High computation performance through efficient access of data structures

High computation performance through efficient access of dat...

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Annual Hawaii International Conference on System Sciences (HICSS)

作者： P.T. Hulina L.D. Coraor O.A. Morean Computer Engineering Program Department of Electrical Engineering Pennsylvania State University USA

The authors propose the use of an access coprocessor (AP) to reduce the adverse effects of the access overhead on the performance of a VLSI processor. The AP offers the possibility of achieving substantial speedup in program execution time by means of concurrency in the access and execute processes, and by the use of special operations to perform efficiently address calculations. System operation is illustrated by means of a matrix multiplication algorithm. A preliminary analysis of the performance of a VLSI processor, with and without the AP, is presented.< >

关键词： High performance computing Data structures Coprocessors Very large scale integration Memory management Data processing computer languages High level languages Concurrent computing System performance

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A VLSI join module

A VLSI join module

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Annual Hawaii International Conference on System Sciences (HICSS)

作者： A.R. Hurson C.R. Petrie J.B. Cheng Computer Engineering Program. Department of Electrical Engineering Pennsylvania State University USA

Some of the previously proposed join operation implementations in several database machines are briefly analyzed. An associative parallel join module and its O(n) associative parallel algorithm are proposed. A VLSI ch... 详细信息

关键词： Very large scale integration Database machines Relational databases Spatial databases Parallel algorithms Application software Hardware Data engineering Design engineering Data security

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Designing fault tolerance capabilities into real-time distributed computer systems

Designing fault tolerance capabilities into real-time distri...

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IEEE Workshop on Future Trends of Distributed Computing Systems

作者： K.H. Kim Computer Engineering Program Department of Electrical Engineering University of California Irvine CA USA

Some of the fault-tolerance schemes that have been established as promising ones for use in real-time distributed computer systems (DCSs) are reviewed. Major issues that remain to be resolved in the 1990s are also discussed. By and large, the design of fault-tolerant real-time DCSs is an immature field. Many of the promising fault tolerance schemes have not been adequately evaluated. It is hoped that many more testbed-based efforts will be made in the field of fault-tolerant real-time distributed computing.< >

关键词： Fault tolerant systems Real time systems Distributed computing Fault tolerance Design engineering Application software Distributed control Control systems Fault diagnosis Navigation

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Approaches to implementation of a repairable distributed recovery block scheme

Approaches to implementation of a repairable distributed rec...

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International Symposium on Fault-Tolerant Computing (FTCS)

作者： K.H. Kim J.C. Yoon Computer Engineering Program Department of Electrical Engineering University of California Irvine CA USA

The authors previously proposed (1984) the basic concept of the distributed recovery block (DRB) scheme as an approach to uniform treatment of hardware and software faults in real-time applications. Design issues that arise in implementing the DRB scheme are discussed together with some promising approaches. Issues in extending the DRB scheme with the capability of reincorporating a repaired node without disrupting the real-time computing service are also discussed. An experimental implementation of the repairable DRB scheme into a real-time distributed computer system (DCS) testbed and subsequent measurement of the system performance demonstrated the fast forward recovery capability and the logical soundness of the scheme.< >

关键词： Hardware Real time systems Application software Distributed computing Distributed control System testing Redundancy Acoustic testing Logic testing System performance

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A quadtree communication structure for fast data searching and distribution

A quadtree communication structure for fast data searching a...

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IEEE Annual International computer Software and Applications Conference (COMPSAC)

作者： W. Lin T.-L. Sheu C.R. Das Computer Engineering Program Department of Electrical Engineering Pennsylvania State University University Park PA USA

Presents a quadtree communication structure and two associated procedures for efficient, contention-free data searching and distribution on the BBN Butterfly parallel processor and its family. The proposed quadtree structure suggests a general approach to mapping a class of parallel algorithms with intensive communication requirements for performing two primitive operations: selecting data from many different sources and distributing data from a single source. While performing these two operations through the quadtree structure, the 'ascend' and 'descend' procedures incur no link conflicts in the Butterfly network. A concrete example of mapping the linear programming algorithm is given to show the effectiveness of the proposed quadtree communication structure.< >

关键词： Switches Linear programming Communication switching Hardware Concurrent computing Distributed computing Parallel algorithms Broadcasting Data engineering Merging

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Evaluation of system BIST using computational performance measures

Evaluation of system BIST using computational performance me...

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IEEE International Test Conference

作者： D.L. Landis D.C. Muha Department of Electrical Engineering Computer Engineering Program Pennsylvania State University University Park PA USA

The impact of built-in self-test (BIST) techniques and system maintenance strategies on the performance of a VLSI processor system is examined. The specific BIST technique used was shown to have a significant influence upon instantaneous and cumulative system reward. It was shown that the additional overhead of the distributed and BILBO approaches is justified for this model when area utilization and cumulative area utilization are considered. For the assumed design parameters, the results presented allow a VLSI system designer to choose an optimal configuration based on system requirements and individual component parameters. The optimal performance will also depend on system and component parameters such as processor failure rates and fault coverage. These results are relevant to the design, evaluation, and optimization of highly reliable, high-performance digital processing systems.< >

关键词： Built-in self-test Circuit testing computer applications Fault tolerant systems Semiconductor device measurement Application software Circuit faults Fault detection Very large scale integration Area measurement

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