This paper addresses the challenge of commonmode voltage (CMV) generation in three-phase two-level back-to-back converters, which are a significant source of electromagnetic interference (EMI) in variable-speed drive ...
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This paper proposes an isolated LCC resonant converter (LCC-RC) designed to deliver a constant output current for LED drivers across a wide range of input voltages by integrating a boost front-end stage with an LCC re...
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General matrix multiplication (GeMM) is a core operation in virtually all AI applications. Systolic array (SA) based architectures have shown great promise as GeMM hardware accelerators thanks to their speed and energ...
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In recent years, we have witnessed an increase in data transfer rates, which requires the development of new communication methods that can handle high-speed data transfer at challenging communication channels. One of...
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ISBN:
(纸本)9798350367003
In recent years, we have witnessed an increase in data transfer rates, which requires the development of new communication methods that can handle high-speed data transfer at challenging communication channels. One of the needs is the transmission of communication over serializer deserializer (SerDes) printed circuit boards (PCBs). which are used to transmit data between chips at high speeds of 10 Gbps and above, using the pulse amplitude modulation with four levels (PAM-4) encoding method, which enables lower losses and relatively low cost. Significant signal degradation is present in high-speed communication systems at SerDes, and inter-symbol interference (ISI) distortion dominates. One of the most effective methods to mitigate ISI distortion is the use of equalizers. The goal of this research is to study the performance of communication between two chips (transmitter/receiver) over SerDes PCB at 100 Gbps using the PAM-4 encoding method with an integrated continuous time linear equalizer (CTLE), feedforward equalizer (FFE), and decision feedback equalizer (DFE). The analysis includes a transmitter/receiver with PAM-4 encoding including the PCB channel response. Further, testing the performance of the combination of different equalizers while defining relevant values and parameters (rate, transmission, convergence rate, and equalizer coefficients). Performance are evaluated using signal-to-noise ratio (SNR) and bit error rate (BER) metrics. We investigated the BER performance for five PCBs of different lengths with analog CTLE and digital FFE-DFE equalizers and found that: For a small number of taps in FFE-DFE, a specific CTLE configuration is optimal, but for an optimal combination of FFEDFE, a different configuration of the CTLE is the best for all PCB lengths. We also show that the longer the PCB length, the more coefficients of the FFE-DFE are needed, consequently, more power is required to compensate for a longer PCB length. The components of your paper [titl
In this paper, a bridgeless buck PFC structure is presented. To Fulfill soft switching for the main switches an auxiliary circuitry is utilized. The main switches of the proposed structure operate under ZVS condition ...
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Image inpainting consists of filling holes or missing parts of an image. Inpainting face images with symmetric characteristics is more challenging than inpainting a natural scene. None of the powerful existing models ...
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This study introduces an obstacle detection system for visual impairment rehabilitation in visually impaired individuals, leveraging YOLOv5 and transfer learning. The methodology comprises four main phases. First phas...
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This work aims to leverage the existing fifth generation (5G) new radio (NR) synchronization signal (SS) burst for network-side integrated sensing and communications (ISAC). A novel density-based clustering of applica...
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This paper is concerned with the event-driven stabilization of Markov jump systems with disturbances based on disturbance observer (DO). First, a DO is employed to estimate the disturbance generated by an exogenous sy...
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This study investigates the combined berth allocation problem (BAP) and quay crane allocation problem (QCAP) while considering a multi-quay setting. First, a mixed integer linear programming mathematical model is deve...
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