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IEEE International Conference on communications (ICC)

作者： Sung-Chan Ko Junghwan Kim Jae-Moung Kim Ji Won Jung Department of Information and Communication National An Dong University Gyeongsangbuk South Korea Department of Electrical Engineering and Computer Sciense University of Tolctlo and Eötvös Lárand University Toledo OH USA Satellite Communications System Division Electronics and Telecommunications Research Institute Taejon South Korea Department of Radio Science and Engineering Korea Maritime University busan South Korea

ISBN: (纸本)0780339258

For the estimation of average bit error rate (BER) of complex digital communication systems, Monte-Carlo (MC) simulation technique has been widely used because of its simplicity. However, it requires excessively long execution time to estimate lower BER. Although this time can substantially be reduced by using importance sampling (IS), IS has not been quite successful in the simulation of practical nonlinear satellite communication systems that typically consist of memory components and forward error correction (FEC) scheme. In this paper, we propose a new algorithm for the simulation of Viterbi decoder using sequentially implemented IS. We then combine it with the efficient importance sampling (EIS) technique to resolve the problems associated with memory. Results from this integration exhibit dramatic reduction of simulation time. Principles of the new simulation method of Viterbi decoding are presented. Details on the integration with EIS are followed with some numerical examples.

关键词： Monte Carlo methods Decoding Bit error rate Viterbi algorithm Computational modeling Satellite communication Forward error correction Discrete event simulation Convolutional codes Digital communication

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Improved extendible hashing with high concurrency

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SYSTEMS AND computerS IN JAPAN 1995年第13期26卷 1-11页

作者： Hirano, Y Satoh, T Miura, F Member NTT Information and Communication Systems Laboratories Yokosuka Japan 238 A research engineer at NIT Information and Communication Systems Laboratories. His research interests include parallel database processing and main memory databases. Mr. Hirano received his B.E. and M.E. degrees in electronic engineering from Kanazawa University in 1987 and 1989 respectively. He is a member of the IEEE Computer Society and Institute of Electronics Information and Communication Engineers of Japan. Nonmember A research engineer at NIT Information and Communication Systems Laboratories. He received his B.E. degree in applied mathematics and physics in 1988 and M.E. degree in application system science in 1990 both from Kyoto University. Mr. Miura is a member of the Information Processing Society of Japan.

We propose an improved extendible hashing scheme and a bucket multi-versioning scheme that achieve a higher concurrency. In our improved extendible hashing, the global depth and directory entries are asynchronously modified to reduce lock conflicts on the directory. Furthermore, bucket multi-versioning enables read-only access to a bucket which is being split. Simulation studies show that these two methods provide an increase in speed in proportion to the number of processors and that they enable concurrent insertions and retrievals to be performed without either affecting the other.

关键词： dynamic hashing extendible hashers concurrency

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Chaos from orbit-flip homoclinic orbits generated in real systems

Chaos from orbit-flip homoclinic orbits generated in real sy...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Hisa-Aki Tanaka S. Oishi K. Horiuchi Department of Electronics and Communication Engineering Waseda University Shinjuku Tokyo Japan Department of Information and Computer Sciences Waseda University Shinjuku Tokyo Japan

A new class of chaotic systems is discovered that are generated in a practical, nonlinear, mutually coupled phase-locked loop (PLL) circuit. Presented theoretical results make it possible to understand experimental results of mutually coupled PLL's on the onset of chaos using the geometry of the invariant manifolds, while the resultant simple geometry and complex dynamics is expected to have applications in other areas, e.g., power systems or interacting bar magnets. Motivated by the numerical study of this system, the topological horseshoe is proven to be generated in the codimension 3 unfolding of a degenerated orbit-flip homoclinic point for this system. Qualitatively different type of bifurcation phenomena are also observed to appear depending on the phase detector (PD) characteristics.

关键词： Chaos Orbits Power system dynamics Coupling circuits Mutual coupling Phase locked loops Geometry Nonlinear dynamical systems Magnets Bifurcation

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FAULT-TOLERANT ASSOCIATE MEMORIES

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SYSTEMS AND computerS IN JAPAN 1995年第7期26卷 1-12页

作者： FUJIWARA, E TANAKA, T Member Faculty of Engineering Tokyo Institute of Technology Tokyo Japan 152 Eui Fujiwara:received his B.S. and M.S. degrees in Electronics Engineering in 1968 and 1970 respectively and his Dr. of Eng. degree in 1981 all from Tokyo Institute of Technology. In 1970 he joined the NTT Musashino Electrical Communication Laboratories and engaged in developing PIPS-1 and PIPS-11 computer systems. In 1988 he joined the Department of Computer Science Tokyo Institute of Technology as an Associate Professor. In 1990 he became a full Professor. He was a Visiting Professor at the Center for Advanced Computer Studies the University of Southwestern Louisiana from June 1985 to July 1986. His current research interests include coding theory for computers fault-tolerant memories VLSI defect-toleranceand WSI systems. He is a co-author ofError Control Coding for Computer Systems(Prentice-Hall1989) EssentiaLF of Error-Correcting Coding Techniques (Academic Press 1990) and other books. Dr. Fujiwara received the Young Engineer Award from the I.E.I.C.E. in 1978 and the Teshima Memorial Research Award in 1991. He is a senior member of the IEEE and a member of the Information Processing Society Japan. Associate Member

Because of its capability of high-speed search, the associative memory (CAM) is expected to be used in a variety of information processing systems. In this paper, novel fault-tolerant techniques which are effective for on-line use are proposed for TLB which is an example of the application of CAM. First, fault and error models of the TLB consisting of the CAM part and the SRAM part are clarified. Then, the fault-tolerant techniques for these faults and errors, such as distance separable technique, cod-ing technique, simplified 1-out-of-n check and graceful degradation, are proposed. The distance separable technique which encodes the data stored in the CAM part is the one which masks the faulty CAM part and prevents errors from propagating to the subsequent circuits. The coding technique checks the one-to-one correspondence between the data in the CAM and those in SRAM by using the SEC-DED code with byte error detection capability, i.e., SEC-DED-SbED code, and at the same time it detects and corrects errors in the data stored in SRAM. The simplified 1-out-of-n check processes association errors. The graceful degradation gives a flag in the faulty memory section and prevents it from being used. The methods proposed in this paper are evaluated from area augmentation and error detection capability perspectives. The results show that the fault-tolerant TLB with 32 virtual address bits, 32 physical address bits and 128 entries gives single fault detection probability of nearly 99 percent with 28 percent area increase.

关键词： CAM TLB DISTANCE SEPARABLE TECHNIQUE CODING TECHNIQUE SIMPLIFIED 1-OUT-OF-N CHECK GRACEFUL DEGRADATION

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An implementation of parallel production systems with two load balancing mechanisms

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SYSTEMS AND computerS IN JAPAN 1995年第14期26卷 1-14页

作者： Miyazaki, J Yokota, H Member School of Information Science Japan Advanced Institute of Science and Technology Ishikawa-ken Japan 923 Received his B.E. degree from Tokyo Institute of Technology Tokyo Japan in 1992 and his M.S. degree from Japan Advanced Institute of Science and Technology (JAIST) Ishikawa Japan in 1994. He is a Ph.D. student at School of Information Science JAIST. His research interests include parallel rule base systems active database systems and high performance I/O systems. He is a member of the Institute of Electronics Information and Communication Engineers of Japan and Information Processing Society of Japan. Received his B.E. M.E. and Dr. of Eng. degrees from Tokyo Institute of Technology in 1980 1982 and 1991 respectively. He joined Fujitsu Ltd. in 1982 and was a researcher at the Institute of New Generation Computer Technology (ICOT) from 1982 to 1986 and at Fujitsu Laboratories Ltd. from 1986 to 1992. He is an Associate Professor of School of Information Science Japan Advanced Institute of Science and Technology (JAIST). HIS research interests include parallel computer architecture for databases and data engineering. He is a member of IPS I.E.I.C.E. JSAI IEEE and ACM.

An implementation method is proposed for parallel production systems on multicomputers, or message-passing computers, to speed up execution time. There have been proposed parallel production systems using hash mechanism, but they cause a skewed load distribution problem. To obtain more efficient balance of load, the method addressed here and named clustered parallel production systems (CPPS) adopts two load balancing strategies: hash and demand-driven. Taking account of the cost of termination detection, the execution time of the CPPS and simple hash method are estimated, and implement on an nCube2. The estimation meets the execution results. The CPPS provides much better load balance to improve scalability.

关键词： parallel production system multicomputer message-passing parallel computer load balancing

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A novel VLSI array design for the discrete Hartley transform using cyclic convolution

A novel VLSI array design for the discrete Hartley transform...

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Proceedings of the 1994 IEEE International Conference on Acoustics, Speech and Signal Processing. Part 2 (of 6)

作者： Gtiot, Jitrn-In Litrt, Chi-Min Jen, Chein-Wei Computer and Communication Research Laboratories Industrial Technology Research Institute Hsinchu30050 Taiwan Dept. of Computer Science and Information Engineering National Chiao Tung University Hsinchu30050 Taiwan Institute of Electronics National Chiao Tung University Hsinchu30050 Taiwan

This paper presents a novel VLSI array design for the 1-D discrete Hartley transform (DHT). Using the similar idea to the Chirp-Z transform, we develop an algorithm which can formulate the 1-D any-length DHT as cyclic convolutions. This algorithm owns higher flexibility in the transform length as compared with the existing approach of Guo, Liu, and Jen (see Proc. IEEE International Conference on Acoustics;Speech, and Signal Processing, p.v.621-v.624, 1992 and IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol.30, p.723-733, Oct. 1992). Moreover, we use the memory-based approach to realize the cyclic convolutions by systolic arrays and implement the multiplications by small ROMs and adders. The presented array not only outperforms the distributed arithmetic (DA) architectures in the hardware area, but also owns low input/output (I/O) cost, power dissipation, high computing speeds and flexibility in transform length. © 1994 IEEE.

关键词： Convolution

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A novel VLSI array design for the discrete Hartley transform using cyclic convolution

A novel VLSI array design for the discrete Hartley transform...

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International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： Jiun-In Guo Chi-Min Liu Chein-Wei Jen Computer & Communication Research Laboratories Industrial Technology and Research Institute Taiwan Department of Computer Science and Information Engineering National Chiao Tung University Taiwan Institute of Electronics National Chiao Tung University Taiwan

ISBN: (纸本)0780317750

This paper presents a novel VLSI array design for the 1-D discrete Hartley transform (DHT). Using the similar idea to the Chirp-Z transform, we develop an algorithm which can formulate the 1-D any-length DHT as cyclic convolutions. This algorithm owns higher flexibility in the transform length as compared with the existing approach of Guo, Liu, and Jen (see Proc. IEEE International Conference on Acoustics; Speech, and Signal Processing, p.v.621-v.624, 1992 and IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol.30, p.723-733, Oct. 1992). Moreover, we use the memory-based approach to realize the cyclic convolutions by systolic arrays and implement the multiplications by small ROMs and adders. The presented array not only outperforms the distributed arithmetic (DA) architectures in the hardware area, but also owns low input/output (I/O) cost, power dissipation, high computing speeds and flexibility in transform length.< >

关键词： Very large scale integration Discrete transforms Signal processing algorithms DH-HEMTs Convolution Chirp Speech processing Acoustic signal processing Array signal processing Circuits

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A general approach to design VLSI arrays for the multi-dimensional discrete Hartley transform

A general approach to design VLSI arrays for the multi-dimen...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Jiun-In Guo Chi-Min Liu Chein-Wei Jen Computer & Communication Research Laboratories Industrial Technology and Research Institute Department of Computer Science and Information Engineering National Chiao Tung University China Institute of Electronics National Chiao Tung University Hsinchu Taiwan

In this paper, a general memory-based approach to design VLSI arrays for the multi-dimensional (M-D) discrete Hartley transform (DHT) with any length is proposed. There are four parts of this approach: (1) a new M-D DHT formulation, (2) cyclic convolution representation, (3) systolic array realization, and (4) memory-based implementation. Deriving a new M-D DHT formulation avoids the undesirable overhead required in formal designs. Taking cyclic convolution provides high computing parallelism and low computation complexity. Using systolic array realisation results in high computing speeds and low I/O cost. Adopting the memory-based implementation yields low hardware cost and low power dissipation. In summary the proposed approach will lead to efficient and high-performance VLSI array designs for the M-D DHT.< >

关键词： Very large scale integration Discrete transforms Hardware Discrete Fourier transforms Convolution Systolic arrays Costs Chirp Concurrent computing Discrete cosine transforms

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BROAD-BAND ISLAND INTERCONNECTION VIA SATELLITE - PERFORMANCE ANALYSIS FOR THE RACE-II CATALYST PROJECT

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INTERNATIONAL JOURNAL OF SATELLITE communicationS 1994年第3期12卷 223-238页

作者： HADJITHEODOSIOU, MH KOMISARCZUK, P COAKLEY, F EVANS, BG SMYTHE, C Centre for Satellite Engineering Research University of Surrey Guildford GU2 5XH U.K. Obtained an M.A. in Electrical and Information Sciences from the University of Cambridge in 1989 and an M.S. in Electrical Engineering from the University of California Irvine in 1991. He is currently a Research Fellow at the Centre for Satellite Research University of Surrey U.K. His research interests include multiple access protocols for VSAT networks voice/data integration in low-bit-rate networks and the use of satellites for the provision of BISDN services. Obtained a B.Sc. in Pure and Applied Physics with Electronics in 1983 and an M.Sc. in Modern Electronics in 1984 from the University of Nottingham U.K. He was a project engineer on the Corporate Data Network for the Central Electricity Generating Board U.K. and then a senior lecturer in communication systems at the University of Greenwich UK. At present he is working on his Ph.D. at the Centre for Satellite Engineering Research (CSER) University of Surrey on the performance of communication systems. Has been Senior Lecturer in the Department of Electrical Engineering University of Surrey since 1984. She is the author (or joint author) of more than 80 research papers. Currently she teaches courses in Telecommunication Networks and Computer Architecture. Her research interests include on-board processing for satellites protocols and performance issues. Received the BSc. and Ph.D. degrees in Electrical Engineering and Microwave Systems from the University of Leeds in 1965/1968. He was British Telecom Lecturer-Reader in Telecommunications Systems at the University of Essex from 1969–1983. In 1983 he was appointed to the Alec Harley Reeves Chair of Information Systems Engineering at the University of Surrey and in 1990 became the first Director of the post-graduate centre for Satellite Engineering Research which houses some 100 researchers. In 1992 he was made a Fellow of the Royal Academy of Engineers in the U.K. and is a Fellow of IEE and a member of IEEE

The use of communication satellites as a possible way of offering broadband island interconnectivity appears to be a very attractive option, as it will enable the provision of an all-digital, transparent service to a number of ATM islands spanning a wide area, accommodating efficiently a variety of traffic demands. The CATALYST Project (RACE II/R2074) is an attempt to demonstrate the applicability and compatibility of satellite technology with the terrestrial BISDN. In this paper we present an overview of the project and focus on an initial study of the expected user performance through the CATALYST network. Our analysis is based upon mathematical and simulation models and describes the end-system to end-system transfer delay for given message lengths. The protocol profiles assume a mix of Novell NetWare and Network File System client/server architectures, which are supported by either the IEEE 802.3/Ethernet or fibre distributed data interface LANs, which are themselves linked via LAN/ATM/satellite interface units. Areas of further investigation, and the implication of our analysis on the actual network architecture, are discussed.

关键词： ASYNCHRONOUS TRANSFER MODE (ATM) BROAD-BAND ISDN SATELLITE communicationS

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FUEL-CELL POWER-PLANTS FOR SURFACE FLEET APPLICATIONS

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NAVAL ENGINEERS JOURNAL 1994年第3期106卷 59-76页

作者： GOUBAULT, P GREENBERG, M HEIDENREICH, T WOERNER, J Philippe Goubault:graduated in 1983 from the “Ecole Nationale Superieure de Techniques Avancees” in Paris with a major in naval architecture. After one year of military service with the French navy he worked as naval architect and program director for the French navy between 1984 and 1988. He was in charge of the development of AGNES200 Surface Effect Ship design which completed its sea trials in 1992. He also was responsible for the construction of five ships (four hydrographic vessels and one experimental MCM vessel) which entered service between 1988 and 1991. He has been involved in a number of projects and studies for the U.S. Navy U.S. Coast Guard and other foreign and domestic customers. At Band Lavis & Associates Inc. Mr. Goubault has expanded the computer tools used to conduct parametric analysis of advanced hullforms and has developed cost-effectiveness assessment tools and methodologies for both commercial and military ships. Mr. Goubault is a member of ASNE. Marc Greenberg:is employed as a cost analyst at the cost and economic analysis branch systems assessment and engineering division Naval Surface Warfare Center. He provides cost estimates and analyses of Navy ship and submarine technologies and has assisted in the development of parametric cost models since 1991. Employed as an electronics engineer by the U.S. Army Information Systems Command from 1989 to 1991 he provided support in simulation design and construction of high frequency and microwave communication systems. Mr. Greenberg received his BS degree in ceramic science and engineering from the Pennsylvania State University May 1987. He is a member of MORS. Todd Heidenreich:is employed in the design analysis and tools branch systems assessment and engineering division of the Carde-rock Division Naval Surface Warfare Center. He is involved as a project naval architect in the conceptual design of future surface ship designs future technology impact assessments and the assessment of current domestic and foreign surface ship desig

This paper describes the results of a study undertaken to determine the impact of fuel cell technology on the design and effectiveness of future naval surface combatants. The study involved the collection of data to characterize four different fuel cell technologies: proton exchange membrane, molten carbonate, phosphoric acid, and solid oxide fuel cells. This information was used to expand current computer models to develop specific fuel cell plants that met the power requirements for several applications on a nominal 5000 Lton destroyer and a nominal 2000 Lton corvette. Each of the fuel cell technologies was incorporated into several applications aboard the destroyer and the corvette. These applications included combinations of centralized and distributed ship service power, and propulsion power. In addition, the impact of fuel cell technology was determined for a ship service power backfit option aboard a DDG-51 class destroyer. The results of the impact on the ship designs were analyzed and a military effectiveness assessment was conducted to address such issues as the impact of fuel cells on mobility, survivability, affordability, and on the environment. The paper identifies which aspects of the fuel cell technologies have the greatest impact upon the ship designs and their operational costs. Recommendations are given for future technology development efforts required to make fuel cells suitable for Navy service.

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