NASA's aggressive plans for extensive deep space exploration with a new generation of unmanned space craft requires a dramatic increase in responsibilities for onboard computing to reduce size, weight, and power t...
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NASA's aggressive plans for extensive deep space exploration with a new generation of unmanned space craft requires a dramatic increase in responsibilities for onboard computing to reduce size, weight, and power to drastically reduce mission costs. No longer will all raw sensor data be transmitted back to Earth but rather only the results from extensive preprocessing to decrease total link capacity by one to three orders of magnitude. A new approach to on board data processing is necessitated by this new expanded mission requirement. Processor-In-Memory (PIM) architecture combines logic and memory on the same integrated circuit to permit direct access to memory row buffers, greatly increasing effective memory bandwidth, reducing overhead and latency, and improving power efficiency. Organizing and managing the resources of PIM based systems is challenging. The PIM-MT architecture is an innovative approach to harnessing the physical resources of PIM technology through a message driven multithreaded virtual execution model. This paper describes the concepts of PIM-MT and its role in future spaceborne computing.
A distributed computing system consists of heterogeneous computing devices, communication networks, operating system services, and applications. As organisations move toward distributed computing environments, there w...
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A distributed computing system consists of heterogeneous computing devices, communication networks, operating system services, and applications. As organisations move toward distributed computing environments, there will be a corresponding growth in distributed applications central to the enterprise. The design, development, and management of distributed applications presents many difficult challenges. As these systems grow to hundreds or even thousands of devices and similar or greater magnitude of software components, it will become increasingly difficult to manage them without appropriate support tools and frameworks. Further, the design and deployment of additional applications and services will be, at best, ad hoc without modelling tools and timely data on which to base design and configuration decisions. This paper presents a framework for management of distributed applications and systems. The framework is based on a set of common management services that support management activities. The services include monitoring, control, configuration, and data repository services. A prototype system built on the framework is described that implements and integrates management applications providing visualisation, fault location, performance monitoring and modelling, and configuration management. The prototype also demonstrates how various management services can be implemented.
In this paper we outline an intelligent hybrid multi-agent architecture for engineering complex systems. The hybrid multi-agent architecture is described at the task structure level. The architecture has been successf...
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In this paper we outline an intelligent hybrid multi-agent architecture for engineering complex systems. The hybrid multi-agent architecture is described at the task structure level. The architecture has been successfully applied in a real time alarm processing and fault diagnosis system in a power system control centre with good performance results.
Neural Networks and Symbolic Knowledge-Based systems each have their strengths and weaknesses. Intelligent systems that fuse these two paradigms overcome a significant number of the weaknesses of each individual parad...
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Neural Networks and Symbolic Knowledge-Based systems each have their strengths and weaknesses. Intelligent systems that fuse these two paradigms overcome a significant number of the weaknesses of each individual paradigm. There are many different approaches in the literature (including research from the author's own group) to fusing these paradigms. A critical evaluation of these approaches is given within the paper.
In order to generate local addresses for an array section A(l:h:s) with block-cyclic distribution, an efficient compiling method is required. In this paper, two local address generation methods for the block-cyclic di...
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ISBN:
(纸本)0780342291
In order to generate local addresses for an array section A(l:h:s) with block-cyclic distribution, an efficient compiling method is required. In this paper, two local address generation methods for the block-cyclic distribution are presented. One is a simple local address generation method that is modified from the virtual-block scheme. The other is a linear-time /spl Delta/M table construction method. The array elements of A(l:h:s) to be accessed at run-time build up a family of lines. By using the equation of the lines, a /spl Delta/M table can be generated in O(k) time. Experimental results show that a simple local address generation method has poor performance but a linear-time /spl Delta/M table generation method is faster than other algorithms in /spl Delta/M table generation time and access time for 10,000 array elements.
In packet-switched networks, queueing of packets at the switches can result when multiple connections share the same physical link. To accommodate a large number of connections, a switch can employ link-scheduling alg...
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In packet-switched networks, queueing of packets at the switches can result when multiple connections share the same physical link. To accommodate a large number of connections, a switch can employ link-scheduling algorithms to prioritize the transmission of the queued packets. Due to the high-speed links and small packet sizes, a hardware solution is needed for the priority queue in order to make the link schedulers effective. But for good performance, the switch should also support a large number of priority levels (P) and be able to buffer a large number of packets (N). So a hardware priority queue design must be both fast and scalable (with respect to N and P) in order to be implemented effectively. In this paper we first compare four existing hardware priority queue architectures, and identify scalability limitations on implementing these existing architectures for large N and P. Based on our findings, we propose two new priority queue architectures, and evaluate them using simulation results from Verilog HDL and Epoch implementations.
Complex applications in domains such as decision support systems and real time systems require a functionality that is achieved by combining the active and temporal database technologies. In this paper we present TALE...
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ISBN:
(纸本)3540612920
Complex applications in domains such as decision support systems and real time systems require a functionality that is achieved by combining the active and temporal database technologies. In this paper we present TALE, a Temporal Active Language and Execution model. TALE is a temporal active database programming language, combined with an execution model that enables a correct and efficient processing of operations. As such, TALE is a step in accommodating software engineering challenges in modern information systems. TALE primitives are presented using examples and an EBNF. The run-time control mechanism of the model is introduced and TALE properties, namely active and temporal capabilities, and reflective programming capabilities are discussed.
Scientific applications often require some strategy for temporary data storage to do the largest possible simulations. The use of virtual memory for temporary data storage has received criticism because of performance...
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ISBN:
(纸本)9780897918541
Scientific applications often require some strategy for temporary data storage to do the largest possible simulations. The use of virtual memory for temporary data storage has received criticism because of performance problems. However, modern virtual memory found in recent operating systems such as Cenju-3/DE give application writers control over virtual memory policies. We demonstrate that custom virtual memory policies can dramatically reduce virtual memory overhead and allow applications to run out-of-core efficiently. We also demonstrate that the main advantage of virtual memory, namely programming simplicity, is not lost.
Scientific applications often require some strategy for temporary data storage to do the largest possible simulations. The use of virtual memory for temporary data storage has received criticism because of performance...
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Scientific applications often require some strategy for temporary data storage to do the largest possible simulations. The use of virtual memory for temporary data storage has received criticism because of performance problems. However, modern virtual memory found in recent operating systems such as Cenju-3/DE give application writers control over virtual memory policies. We demonstrate that custom virtual memory policies can dramatically reduce virtual memory overhead and allow applications to run out-of-core efficiently. We also demonstrate that the main advantage of virtual memory, namely programming simplicity, is not lost.
In this paper, we show the relevance of fuzzy systems in an integrated symbolic-subsymbolic architecture, GENUES (generic neuro-expert system), for information processing. Fuzzy logic is used for modelling knowledge i...
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In this paper, we show the relevance of fuzzy systems in an integrated symbolic-subsymbolic architecture, GENUES (generic neuro-expert system), for information processing. Fuzzy logic is used for modelling knowledge in different phases of the GENUES architecture. As an illustration we show the application of fuzzy logic in the decision phase and post-processing phase of GENUES for power system fault diagnosis.
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