The article researches the problem of self-timed (ST) binary counter implementation. ST circuits demonstrate correct operation over a much wider range of supply voltage and ambient temperature, in contrast to synchron...
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Self-timed (ST) circuits have a number of advantages over synchronous counterparts. They utilize natural interaction between digital units based on data availability. Combinational ST circuits use redundant coding of ...
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Self-Timed circuits are optimal for implementing computing systems operating under extreme conditions. They function reliably under any changes in environmental and power conditions, detect all constant faults, and ar...
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Field programmable gate arrays (FPGAs) serve as a convenient tool for prototyping and debugging developed digital circuits. Their circuitry is optimized for synchronous unit implementation. computer-aided design syste...
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Self-timed circuits have a number of advantages over synchronous counterparts. They are hazard-free under any conditions, and delay insensitive (their behavior does not depend on the cell's delays). They also dete...
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The current trend in microelectronics is to develop energy-efficient, reliable digital devices for control and life support systems with various complexities. The operation of digital circuits in adverse environmental...
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Self-timed (ST) circuits have a number of advantages over synchronous counterparts. They utilize natural interaction between digital units based on data availability. Combinational ST circuits use redundant coding of ...
Self-timed (ST) circuits have a number of advantages over synchronous counterparts. They utilize natural interaction between digital units based on data availability. Combinational ST circuits use redundant coding of information and a two-phase operating discipline, which makes it possible to detect the successful circuit switching completion in each phase. The combinational ST circuit synthesis has been well studied, formalized, and implemented in several existing computer-aided design systems for asynchronous digital units. It is based on dualizing the logical function system in order to convert single information signals into dual-rail signals with a null or unit spacer and supplementing an additional indication subcircuit that detects the completion of ST circuit switching into the current phase. The synthesis of ST circuits with memory is less amenable to formalization. The paper considers the problem of implementing typical ST units with memory, namely latches and flip-flops. It analyzes ST latch and flip-flop implementation features and their interaction with the combinational environment, which requires dual-rail coding of information signals, and offers effective circuit solutions that ensure the adequacy of their behavior in relation to synchronous counterparts.
Artificial intelligence systems operating in the sequential decision making paradigm are inevitably required to do effective spatio-temporal processing. The memory models for such systems are often required not just t...
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The article shows the basic principles, methods and practice of creating an expert information system - a system of knowledge bases that provides an assessment of the effectiveness of advanced research in aerospace (E...
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The article researches the problem of self-timed (ST) binary counter implementation. ST circuits demonstrate correct operation over a much wider range of supply voltage and ambient temperature, in contrast to synchron...
The article researches the problem of self-timed (ST) binary counter implementation. ST circuits demonstrate correct operation over a much wider range of supply voltage and ambient temperature, in contrast to synchronous counterparts. The reason for this is hardware redundancy, two-phase operating discipline and mandatory acknowledging of the switch completion of all circuit cells in each phase of circuit operation. As a result, ST circuits operate stably no matter the cell delays. Due to their simpler indication, serial ST counters have less hardware redundancy than combinational ST circuits. However, they require the specific procedure organization to implement ST preset. The article examines the circuitry basis for the ST counter implementation and proposes a schematic preset realization ensuring its self-timing and optimal hardware complexity.
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