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Combined Measurement of the Higgs Boson Mass in pp Collisions at s=7 and 8 TeV with the ATLAS and CMS Experiments

Physical Review Letters 2015年第19期114卷 191803-191803页

作者： G. Aad B. Abbott J. Abdallah O. Abdinov R. Aben M. Abolins O. S. AbouZeid H. Abramowicz H. Abreu R. Abreu Y. Abulaiti B. S. Acharya L. Adamczyk D. L. Adams J. Adelman S. Adomeit T. Adye A. A. Affolder T. Agatonovic-Jovin J. A. Aguilar-Saavedra S. P. Ahlen F. Ahmadov G. Aielli H. Akerstedt T. P. A. Åkesson G. Akimoto A. V. Akimov G. L. Alberghi J. Albert S. Albrand M. J. Alconada Verzini M. Aleksa I. N. Aleksandrov C. Alexa G. Alexander T. Alexopoulos M. Alhroob G. Alimonti L. Alio J. Alison S. P. Alkire B. M. M. Allbrooke P. P. Allport A. Aloisio A. Alonso F. Alonso C. Alpigiani A. Altheimer B. Alvarez Gonzalez D. Álvarez Piqueras M. G. Alviggi B. T. Amadio K. Amako Y. Amaral Coutinho C. Amelung D. Amidei S. P. Amor Dos Santos A. Amorim S. Amoroso N. Amram G. Amundsen C. Anastopoulos L. S. Ancu N. Andari T. Andeen C. F. Anders G. Anders J. K. Anders K. J. Anderson A. Andreazza V. Andrei S. Angelidakis I. Angelozzi P. Anger A. Angerami F. Anghinolfi A. V. Anisenkov N. Anjos A. Annovi M. Antonelli A. Antonov J. Antos F. Anulli M. Aoki L. Aperio Bella G. Arabidze Y. Arai J. P. Araque A. T. H. Arce F. A. Arduh J-F. Arguin S. Argyropoulos M. Arik A. J. Armbruster O. Arnaez V. Arnal H. Arnold M. Arratia O. Arslan A. Artamonov G. Artoni S. Asai N. Asbah A. Ashkenazi B. Åsman L. Asquith K. Assamagan R. Astalos M. Atkinson N. B. Atlay B. Auerbach K. Augsten M. Aurousseau G. Avolio B. Axen M. K. Ayoub G. Azuelos M. A. Baak A. E. Baas C. Bacci H. Bachacou K. Bachas M. Backes M. Backhaus E. Badescu P. Bagiacchi P. Bagnaia Y. Bai T. Bain J. T. Baines O. K. Baker P. Balek T. Balestri F. Balli E. Banas Sw. Banerjee A. A. E. Bannoura H. S. Bansil L. Barak S. P. Baranov E. L. Barberio D. Barberis M. Barbero T. Barillari M. Barisonzi T. Barklow N. Barlow S. L. Barnes B. M. Barnett R. M. Barnett Z. Barnovska A. Baroncelli G. Barone A. J. Barr F. Barreiro J. Barreiro Guimarães da Costa R. Bartoldus A. E. Barton P. Bartos A. Bassalat A. Basye R. L. Bates S. J. Batista J. R. Batley M. Battaglia M. Bauce F. Bauer H. S. Bawa J. B. Beach CPPM Aix-Marseille Université and CNRS/IN2P3 Marseille France Homer L. Dodge Department of Physics and Astronomy University of Oklahoma Norman Oklahoma USA Institute of Physics Academia Sinica Taipei Taiwan Institute of Physics Azerbaijan Academy of Sciences Baku Azerbaijan Nikhef National Institute for Subatomic Physics and University of Amsterdam Amsterdam Netherlands Department of Physics and Astronomy Michigan State University East Lansing Michigan USA Department of Physics University of Toronto Toronto Ontario Canada Raymond and Beverly Sackler School of Physics and Astronomy Tel Aviv University Tel Aviv Israel Department of Physics Technion: Israel Institute of Technology Haifa Israel CERN Geneva Switzerland Department of Physics Stockholm University Sweden The Oskar Klein Centre Stockholm Sweden INFN Gruppo Collegato di Udine Sezione di Trieste Udine Italy ICTP Trieste Italy AGH University of Science and Technology Faculty of Physics and Applied Computer Science Krakow Poland Physics Department Brookhaven National Laboratory Upton New York USA Department of Physics Northern Illinois University DeKalb Illinois USA Fakultät für Physik Ludwig-Maximilians-Universität München München Germany Particle Physics Department Rutherford Appleton Laboratory Didcot United Kingdom Oliver Lodge Laboratory University of Liverpool Liverpool United Kingdom Institute of Physics University of Belgrade Belgrade Serbia Laboratorio de Instrumentacao e Fisica Experimental de Particulas-LIP Lisboa Portugal Departamento de Fisica Teorica y del Cosmos and CAFPE Universidad de Granada Granada (Spain) Portugal Department of Physics Boston University Boston Massachusetts USA Joint Institute for Nuclear Research JINR Dubna Dubna Russia INFN Sezione di Roma Tor Vergata Roma Italy Dipartimento di Fisica Università di Roma Tor Vergata Roma Italy Fysiska institutionen Lunds universitet Lund Sweden International Center for Elementary Particle Physics and Depart

A measurement of the Higgs boson mass is presented based on the combined data samples of the ATLAS and CMS experiments at the CERN LHC in the H→γγ and H→ZZ→4ℓ decay channels. The results are obtained from a simultaneous fit to the reconstructed invariant mass peaks in the two channels and for the two experiments. The measured masses from the individual channels and the two experiments are found to be consistent among themselves. The combined measured mass of the Higgs boson is mH=125.09±0.21 (stat)±0.11 (syst) GeV.

关键词： HIGGS bosons RESEARCH COLLISIONS (Nuclear physics) ATLAS (computer program language) REST mass (Relativity) BOSONS

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The Relationship between Diagnostic Coverage and Proof Test Interval for 1oo2 and 1oo2D architectures

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IFAC Proceedings Volumes 2012年第24期45卷 181-184页

作者： İlker üstoğlu özgür T. Kaymakçı Josef Börcsök Yıldız Technical University Davutpaşa Campus A209 34220 34220 Esenler İstanbul TURKEY (Tel: +90-535-418-22-64 ) Yıldız Technical University Davutpaşa Campus A210 34220 34220 Esenler İstanbul TURKEY University Kassel Faculty of Electrical Engineering/Computer Science Department of Computer Architecture and System Programming Wilhelmshöher Allee 71 34121 Kassel GERMANY

In order to measure the effectiveness of safety protection systems there are several design parameters. Diagnostic coverage factor is one of the most important parameter which influences all architectures. In this short paper the relationship between PFD avg , DC and T I are presented. 1oo2 and 1oo2D architectures are considered as examples.

关键词： Functional safety 1002 architecture

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Functional framework and hardware platform for dependability study in short range wireless embedded systems

Functional framework and hardware platform for dependability...

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2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 2011

作者： Senouci, B. Annema, A.J. Bentum, M.J. Kerkhoff, H.G. Integrated Circuit Design Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands Telecommunication Engineering Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands Computer Architecture for Embedded Systems Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands

ISBN: (纸本)9780769544793

A new direction in short-range wireless applications has appeared in the form of high-speed data communication devices for distances of a few meters. Behind these embedded applications, a complex Hardware/Software architecture is built. Dependability is one of the major challenges in these systems. Obviously in such systems, the attribute reliability has to be investigated for various components and at different abstractions levels. This paper presents a hardware platform for wireless system dependability analysis as an alternative for the time consuming global system simulation technique. The platform is built using several instances of one of the commercial FPGA platforms available on the market place. Based on this platform we introduce a new methodology and a flow to investigate the different parts of system dependability at different abstraction levels. The benefits to use the proposed methodology are two fold: first it takes care of the whole system (HW/SW part, mixed RF and wireless part) and second, the hardware platform enables to explore the application's reliability under real environmental conditions in order to study the effect of the environment threats on the system. © 2011 IEEE.

关键词： Abstracting

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Data transmission via erasure type channels protected by linear codes

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Journal of Physics: Conference Series 2012年第1期364卷

作者： H D Wacker P Pendli J Börcsök To whom any correspondence should be addressed University Kassel Faculty of Electrical Engineering/Computer Science Department of Computer Architecture and System Programming Wilhelmshöher Allee 71 34121 Kassel

The paper is concerned with data transmission via channels composed of a memoryless binary symmetric channel and the erasure channel of Peter Elias. Channels of this type play an important role in modelling different types of networks especially wireless networks, and have been investigated using, amongst others, the theory of Markov chains. Channel Capacities and network flows have been determined. The authors focus their interest on some aspects of coding theory. They assume the data transmission to be protected by a linear code, a CRC for example, and determine the probability of undetected error of the code. They then consider redundant transmission via two or more channels with bit inversion, and calculate the probability of undetected error. They prove some inequalities that are useful instruments to estimate the rate of transmission errors and to determine safety integrity levels according to the standards. Finally the authors apply their results to Bluetooth channels suffering from different types of noise.

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A parallel Ray Tracing architecture suitable for application-specific hardware and GPGPU implementations

A parallel Ray Tracing architecture suitable for application...

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2011 14th Euromicro Conference on Digital System Design: architectures, Methods and Tools, DSD 2011

作者： Nery, Alexandre S. Nedjah, Nadia Franca, Felipe M.G. Jozwiak, Lech LAM - Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado Rio de Janeiro Brazil Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology Netherlands

ISBN: (纸本)9780769544946

The Ray Tracing rendering algorithm can produce high-fidelity images of 3-D scenes, including shadow effects, as well as reflections and transparencies. This is currently done at a processing speed of at most 30 frames per second. Therefore, actual implementations of the algorithm are not yet suitable for interactive real-time rendering, which is required in games and virtual reality based applications. Fortunately, the algorithm allows for massive parallelization of its computations. In this paper, we present a parallel architecture for ray tracing based on a uniform spatial subdivision of the scene and exploiting an embedded computation of ray-triangle intersections. This approach allows for a significant acceleration of intersection computations, as well as, a reduction of the total number of the required intersections checks. Furthermore, it allows for these checks to be performed in parallel and in advance for each ray. In this paper we discuss and analyze an ASIP-based implementation using FPGAs and a GPGPU-based parallel implementation of the proposed architecture. The performance of both implementations are reported and compared." © 2011 IEEE.

关键词： Ray tracing

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Fraud Detection in Interoperable Information Systems

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computer Technology and Application 2011年第7期2卷 530-538页

作者： Saga Mladenovie Marko Rosic Maja Stula Computer Science Department Faculty of Science University of Split Split 21000 Croatia Faculty of Electrical Engineering Mechanical Engineering and Naval Architecture University of Split Split 21000 Croatia

Interoperability is broad and complex subject being the most critical issue facing businesses that need to access information from multiple systems. The concept of unwanted interoperability can result in fault decision making based on counterfeit data produced by hostile interoperable system. Research in this paper is based on highway toll collection system analysis as representative of hierarchical heterogeneous systems where integration becomes more important than development due to the short time in disposal between the contract signature and implementation. Unwanted interoperability detect mechanism is presented using information collected from different information system levels.

关键词： Unwanted interoperability hierarchical system toll collection fraud.

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Functional Framework and Hardware Platform for Dependability Study in Short Range Wireless Embedded Systems

Functional Framework and Hardware Platform for Dependability...

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IEEE International Mixed-Signals, Sensors, and Systems Test Workshop, IMS3TW

作者： Benaouneur Senouci Anne-Johan Annema Mark Bentum Hans G. Kerkhoff Telecommunication Engineering Group Computer Architecture for Embedded Systems Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands Integrated Circuit Design Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands Telecommunication Engineering Group University of Twente Enschede Netherlands Computer Architecture for Embedded Systems Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands

关键词： Wireless communication Hardware Reliability System-on-a-chip computer architecture Libraries Embedded systems

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Hardware reuse in modern application-specific processors and accelerators

Hardware reuse in modern application-specific processors and...

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2011 14th Euromicro Conference on Digital System Design: architectures, Methods and Tools, DSD 2011

作者： Nery, Alexandre S. Jozwiak, Lech Lindwer, Menno Cocco, Mauro Nedjah, Nadia França, Felipe M.G. LAM - Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado do Rio de Janeiro Brazil Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology Netherlands Silicon Hive - Intel UMG Netherlands

ISBN: (纸本)9780769544946

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-) configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse. © 2011 IEEE.

关键词： Multiobjective optimization

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Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not?

Towards an ESL design framework for adaptive and fault-toler...

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2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2011

作者： Cannella, Emanuele Di Gregorio, Lorenzo Fiorin, Leandro Lindwer, Menno Melonr, Paolo Neugebauer, Olaf Pimentel, Andy Leiden Institute of Advanced Computer Science Leiden University Netherlands Lantiq Deutschland GmbH Neubiberg Germany ALaRI Faculty of Informatics University of Lugano Switzerland Silicon Hive BV High Tech Campus 83 5656 AG Eindhoven Netherlands DIEE Department of Electrical and Electronic Engineering University of Cagliari Cagliari Italy Informatik Centrum Dortmund Joseph-von-Fraunhofer-Str. 20 Dortmund Germany Computer Systems Architecture Group Informatics Institute University of Amsterdam Netherlands

ISBN: (纸本)9781457721236

The MADNESS project aims at the definition of innovative system-level design methodologies for embedded MP-SoCs, extending the classic concept of design space exploration in multi-application domains to cope with high heterogeneity, technology scaling and system reliability. The main goal of the project is to provide a framework able to guide designers and researchers to the optimal composition of embedded MPSoC architectures, according to the requirements and the features of a given target application field. The proposed approach will tackle the new challenges, related to both architecture and design methodologies, arising with the technology scaling, the system reliability and the ever-growing computational needs of modern applications. The methodologies proposed with this project act at different levels of the design flow, enhancing the state-of-the art with novel features in system-level synthesis, architectural evaluation and prototyping. Support for fault resilience and efficient adaptive runtime management is introduced at hardware and middleware level, and considered by the system-level synthesis as one of the optimization factors to be taken into account. This paper presents the first stable results obtained in the MADNESS project, already demonstrating the effectiveness of the proposed methods. © 2011 IEEE.

关键词： Middleware

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A parallel architecture for ray-tracing with an embedded intersection algorithm

A parallel architecture for ray-tracing with an embedded int...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Alexandre S. Nery Nadia Nedjah Felipe M.G. França Lech Jozwiak LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhovan University of Technology Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro (UERJ) Brazil

Real time rendering of three-dimensional scenes in Ray Tracing is a hard problem. However, parallel implementations have been enabling real time performance, as the algorithm can be highly parallelized. Thus, a custom parallel design in hardware is likely to achieve a good performance. In this paper, we further improve the GridRT architecture overall performance by embedding the ray-triangle intersection computation into the precessing elements that form the architecture. Low cost and high rendering performance are the main concerns in this novel design. The results show that the execution time of each intersection computation is reduced by at least 50%, while the area cost is practically unchanged or even reduced when compared to the original GridRT implementation.

关键词： Ray tracing Registers Equations USA Councils Mathematical model Parallel architectures

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