In this paper, we describe and analyze the architecture of the proposed Debug Event Distribution Interconnect (EDI). The EDI transmits debug events, which are 1-bit signals, between debug entities in different areas o...
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In this paper, we describe and analyze the architecture of the proposed Debug Event Distribution Interconnect (EDI). The EDI transmits debug events, which are 1-bit signals, between debug entities in different areas of the Network-on-Chip based Multi-Processor System-on-Chip. The EDI replicates the NoC topology with an EDI node instantiated for each underlying NoC data module. Contention in the EDI node is handled by replicating the EDI in layers. The EDI generation is automatic, and uses as input the cross-triggering patterns that are not required to follow the communication patterns in the NoC. The generation and routing tool is also presented in this paper. The EDI is evaluated with four different implementations varying complexity and handling of contention. The area of a single EDI Layer is around 0.9% of the area occupied by the tested NoCs, using the lower area implementation. These results show that the proposed implementation of the EDI incurs low cost on the overall system.
This paper presents the design and simulation for a pierce oscillator using CMOS MEMS SAW resonator. The MEMS resonator utilizes surface acoustic waves to generate resonant frequencies of 600MHz and 900MHz. The MEMS r...
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This paper presents the design and simulation for a pierce oscillator using CMOS MEMS SAW resonator. The MEMS resonator utilizes surface acoustic waves to generate resonant frequencies of 600MHz and 900MHz. The MEMS resonator is fully compatible with CMOS technology, allowing the possibility of full integration with circuits. The pierce circuit topology was chosen as a sustaining circuit, connected to the resonator to form an oscillator. For simulation purposes, the CMOS MEMS SAW resonator was modeled using its RLC equivalent circuit. The oscillator produces transient oscillation of 300mV peak to peak voltage. The phase noise performance for 600MHz oscillator is -70dBc/Hz at 100 kHz and consume 1.17mW power. The 900MHz oscillator has achieved -63dBc/Hz phase noise at 100 kHz offset frequency and consume about 1.62mW power.
Today object-oriented programming (OOP) is becoming more and more popular than ever, due to Internet and network computing, and need for resource sharing. Java becomes attractive because of its appealing features such...
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Today object-oriented programming (OOP) is becoming more and more popular than ever, due to Internet and network computing, and need for resource sharing. Java becomes attractive because of its appealing features such as platform independence and code reusability. However, Java has lower performance than conventional programming languages due to its real-time execution overheads in the layer of Java Virtual Machine (JVM). With increasing performance through higher clock speed or multi-cores, software virtual machines are still needed to run on top of the operating system to execute Java, reducing the effect of the hardware performance improvements. This research proposes a high-performance computer architecture with hybrid system co-design for Java processing. Our FPGA model implemented in VHDL, jHISC, originates hardware support for object-oriented bytecodes, object referencing and method invocation. Moreover, baseline compiler is developed to construct the core structure and to ensure the architecture compatible to the JVM specifications. The project is at present version 4, which is target for mobile and embedded computing. Comparing with the products by Sun Microsystems through evaluation based on SPEC JVM98 benchmark, jHISC V4.0 provide overall performance gain of around 137% over HotSpot JVM and 102% to 1351% over picoJava II.
We report on the design, fabrication and characterisation of submicron silicon-on-insulator strip waveguides at a 3.74 μm wavelength. Experimental results for 1×2 multi-mode interference splitters are also given.
We report on the design, fabrication and characterisation of submicron silicon-on-insulator strip waveguides at a 3.74 μm wavelength. Experimental results for 1×2 multi-mode interference splitters are also given.
Energy resource constraints inherent in wireless sensor network deployments limit the amount of data that can be transported to a destination sink. An alternative strategy that could be invoked to address this issue i...
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We present experimental evaluations of human-induced perturbations on received-signal-strength-(RSS-) based ranging measurements for cooperative mobile positioning. To the best of our knowledge, this work is the first...
Owing to the uncertainty of transmission opportunities between mobile nodes, the routing in delay-tolerant networks (DTNs) exploits the mechanism of opportunistic forwarding. Energy-efficient algorithms and policies f...
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Owing to the uncertainty of transmission opportunities between mobile nodes, the routing in delay-tolerant networks (DTNs) exploits the mechanism of opportunistic forwarding. Energy-efficient algorithms and policies for DTN are crucial to maximizing the message delivery probability while reducing the delivery cost. In this contribution, we investigate the problem of energy-efficient optimal beaconing control in a DTN. We model the message dissemination under variable beaconing rate with a continuous-time Markov model. Based on this model, we then formulate the optimization problem of the optimal beaconing control for epidemic routing and obtain the optimal threshold policy from the solution of this optimization problem. Furthermore, through extensive numerical results, we demonstrate that the proposed optimal threshold policy significantly outperforms the static policy with constant beaconing rate in terms of system energy consumption savings.
computer vision is a field that includes methods for acquiring, processing, analyzing and understanding images. In the embedded world, computer vision applications have to fight with limited processing power and limit...
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computer vision is a field that includes methods for acquiring, processing, analyzing and understanding images. In the embedded world, computer vision applications have to fight with limited processing power and limited resources to achieve optimized algorithms and high performance. This paper presents work on implementing a human tracking system on both Intel based PC platform and embedded systems to optimize the algorithms for high performance. The algorithms are benchmarked on the Intel platform processor and BeagleBoard xM baed on low-power Texas Instruments (TI) DM3730 ARM processor. Functions and library in OpenCV which developed by Intel Corporation was utilized for building the human tracking algorithms.
The conventional design of home security systems typically monitors only the property and lacks physical control aspects of the house itself. Also, the term security is not well defined because there is a time delay b...
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The conventional design of home security systems typically monitors only the property and lacks physical control aspects of the house itself. Also, the term security is not well defined because there is a time delay between the alarm system going on and actual arrival of the security personnel. This paper discusses the development of a home security and monitoring system that works where the traditional security systems that are mainly concerned about curbing burglary and gathering evidence against trespassing fail. The paper presents the design and implementation details of this new home control and security system based on field programmable gate array (FPGA) The user here can interact directly with the system through a web-based interface over the Internet, while home appliances like air conditioners, lights, door locks and gates are remotely controlled through a user-friendly web page. An additional feature that enhances the security aspect of the system is its capability of monitoring entry points such as doors and windows so that in the event any breach, an alerting email message is sent to the home owner instantly.
Path loss model is generally used to relate distance and signal strength in wireless applications. This has been widely implemented in ranging, localization, and location tracking systems. A range of extension models ...
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ISBN:
(纸本)9781467308946
Path loss model is generally used to relate distance and signal strength in wireless applications. This has been widely implemented in ranging, localization, and location tracking systems. A range of extension models have been proposed to enhance the performance for various environments and applications. Nevertheless, path loss exponent remains its significance as the main factor in the model regardless of how the model is varied. Based on the nature as an exponent of the model, inaccurate path loss exponent amplifies the error if it is used to estimate distance from received signal strength. Therefore, measurement of accurate value for path loss exponent becomes very important as it directly influences the output of distance estimation. Researchers have been studying the methods of measuring accurate path loss exponent in various environments. Instead of emphasizing the calculation process, this paper focuses more on the allocation of transmitters and receivers, and the arrangement among them. From the results obtained from experiments, properly arranged transmitter and receiver nodes provides better estimation of the path loss exponent. Based on the results, this paper also proposes a suitable nodes arrangement scheme for path loss exponent estimation.
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