When a large Petri net system is implemented, several LSI Petri net controllers are used and connected in order to build a whole system. For this purpose, the authors propose a new Petri net controller, which can hold...
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When a large Petri net system is implemented, several LSI Petri net controllers are used and connected in order to build a whole system. For this purpose, the authors propose a new Petri net controller, which can hold much more places than the one proposed before. It also has the new control of tokens for kill-arc and shared-places among sub Petri nets are also proposed. Four accessible registers of tokens makes it possible to access four tokens at the same time, so one can use place-numbers instead of bit-patterns of places as used by the previous controller. This reduces the memory to log n/n of the previous. The new control of tokens makes it easy to keep consistency of tokens among a group of sub Petri net controllers. One can implement LSI Petri net controllers for several time larger Petri nets than previous ones and it is as fast as previous controllers.
Conventional absorbing boundary conditions (ABC's) are used for cubic-cell finite-difference time-domain (FDTD) grids, but not in noncubic cell time-domain grids, We propose an algorithm to apply perfectly matched...
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Conventional absorbing boundary conditions (ABC's) are used for cubic-cell finite-difference time-domain (FDTD) grids, but not in noncubic cell time-domain grids, We propose an algorithm to apply perfectly matched layer (PML) ABC to the noncubic cell time-domain method, The numerical experiments are conducted of the accuracy of the PML in a regular triangle cell grid versus standard second-order Mur and PML ABC's in a square-cell FDTD grid, The PML global error is about 10(-3) of the former and about three times of the latter, According to the convergent characteristics this algorithm is equivalent to that of applying PML ABC to the FDTD method.
This paper presents the design of a low cost, test processor ASIC chip implementing multiple seed, multiple polynomial linear feedback shift register (MPMSLFSR). User programmable seed and feedback connection can be s...
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This paper presents the design of a low cost, test processor ASIC chip implementing multiple seed, multiple polynomial linear feedback shift register (MPMSLFSR). User programmable seed and feedback connection can be set in the pattern generator of the chip to improve fault coverage. The ASIC also supports scan-path testing. It can also be used to design external IC tester.
The authors propose a Petri net control system to implement a large Petri net. When a large Petri net is to be implemented, it is divided into several smaller sub nets and each sub net is implemented by a Petri net co...
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The authors propose a Petri net control system to implement a large Petri net. When a large Petri net is to be implemented, it is divided into several smaller sub nets and each sub net is implemented by a Petri net controller made of LSI. So this system consists of a group of Petri net controllers and a communication controller. In order that a group of sub nets working as an original large net, it is important to keep the consistency of tokens among these sub-nets. Here, the authors present a revised Petri net controller to make a divide-and-rule system. A register, called the FCTR (fire check transition register), is added to hold fireable transition. This makes it easy for each controller to check the consistency of tokens in places shared among sub-net controllers. A new communication protocol among controllers and its hardware implementation are also proposed. The revised Petri net controller will be implemented with little increase in hardware.
In this paper, the geometric learning algorithm (GLA) is proposed for an elementary perceptron which includes a single output neuron. The GLA is a modified version of the affine projection algorithm (APA) for adaptive...
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ISBN:
(纸本)0780341236
In this paper, the geometric learning algorithm (GLA) is proposed for an elementary perceptron which includes a single output neuron. The GLA is a modified version of the affine projection algorithm (APA) for adaptive filters. The weights update vector is determined geometrically towards the intersection of the k hyperplanes which are perpendicular to patterns to be classified. k is the order of the GLA. In the case of the APA, the target of the coefficients update is a single point which corresponds to the best identification of the unknown system. On the other hand, in the case of the GLA, the target of the weights update is an area, in which all the given patterns are classified correctly. Thus, their convergence conditions are different. In this paper, the convergence condition of the 1st order GLA for 2 patterns is theoretically derived. The new concept ''the angle of the solution area'' is introduced. The computer simulation results support that this new concept is a good estimation of the convergence properties.
Since the layout compaction problem is dual to the minimum cost flow problem, flow algorithms can be applicable to the layout compaction. In this paper, an existing flow algorithm is investigated in terms of the layou...
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Since the layout compaction problem is dual to the minimum cost flow problem, flow algorithms can be applicable to the layout compaction. In this paper, an existing flow algorithm is investigated in terms of the layout compaction, and a fast flow algorithm is devised on the basis of the primal-dual method. Experimental results show that the proposed algorithm is the fastest dedicatedly for the compaction problem.
We consider M-ary, multitrack runlength limited (d,k) constrained channels with and without clock redundancy. We calculate the Shannon capacities of these channels and present some simple 100% efficient codes. To comp...
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We consider M-ary, multitrack runlength limited (d,k) constrained channels with and without clock redundancy. We calculate the Shannon capacities of these channels and present some simple 100% efficient codes. To compute capacity a constraint graph equivalent to the usual runlength limited constraint graph is used. The introduced graph model has a vertex labeling independent of N, the number of tracks to be written on (in parallel), which provides computational savings when the number of tracks is large. We show that increasing the number of tracks provides a significant increase of per-track capacity for more restrictive clocking, i.e. When k d.
In this paper, an experimental study on robust control of bending and torsional vibrations and contact force of a one-link flexible arm is discussed. The flexible arm carries a symmetric rigid tip body, of which the m...
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In this paper, an experimental study on robust control of bending and torsional vibrations and contact force of a one-link flexible arm is discussed. The flexible arm carries a symmetric rigid tip body, of which the mass center lies on the center axis of the arm. We derive dynamic equations of the joint angle, the vibrations of the flexible link, and the contact force. On the basis of a finite-dimensional modal model of a distributed-parameter system, robust controllers are constructed. Some experimental results are shown.
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