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International Joint Conference on Computer Science and Software engineering (JCSSE)

作者： Khanob Thongkhome Chalermwat Thanavijitpun Somsak Choomchuay College of Data Storage Technology and Applications King Mongkut's Institute of Technology Ladkrabang Bangkok Thailand Department of Electronic Engineering Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang Bangkok Thailand

This paper describes a high effective AES core hardware architecture for implementing it to encrypt/decrypt the data in portable hard disk drive system that apply to effectively in the terms of speed, scale size and power consumption to comply with minimum speed of 5 Gbps (USB3.0). We proposed the 128 bits data path of two different AES architectures design, Basic Iterative AES, which reuses the same hardware for all the ten iterations and, One Stage Sub Pipelined AES, with one stage of outer pipelining in the data blocks that both of them are purely 128 bits data path architecture that different from the previous public paper. The implementation result on the targeted FPGA, the basic iterative AES encryption can offer the throughput of 3.85 Gbps at 300 MHz and one stage sub pipelined AES can offer the throughput to increase the efficiency of 6.2 Gbps at 481 MHz clock speed.

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Plasmonics: Plasmon‐Enhanced Sub‐Wavelength Laser Ablation: Plasmonic Nanojets (Adv. Mater. 10/2012)

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Advanced Materials 2012年第10期24卷

作者： Ventsislav K. Valev Denitza Denkova Xuezhi Zheng Arseniy I. Kuznetsov Carsten Reinhardt Boris N. Chichkov Gichka Tsutsumanova Edward J. Osley Veselin Petkov Ben De Clercq Alejandro V. Silhanek Yogesh Jeyaram Vladimir Volskiy Paul A. Warburton Guy A. E. Vandenbosch Stoyan Russev Oleg A. Aktsipetrov Marcel Ameloot Victor V. Moshchalkov Thierry Verbiest Molecular Electronics and Photonics INPAC Katholieke Universiteit Leuven BE‐3001 Belgium Superconductivity and Magnetism & Pulsed Fields Group INPAC Katholieke Universiteit Leuven BE‐3001 Belgium SAT‐TELEMIC Katholieke Universiteit Leuven B‐3001 Leuven Belgium Advanced Concepts Group Data Storage Institute 5 Engineering Drive I 117608 Singapore Laser Zentrum Hannover e.V. D‐30419 Hanover Germany Department of Solid State Physics Faculty of Physics Sofia University Sofia 1164 Bulgaria London Centre for Nanotechnology University College London 17‐19 Gordon Street London WC1H 0AH United Kingdom Department of Electronic and Electrical Engineering University College London Torrington Place London WC1E 7JE United Kingdom Dept. Metallurgy and Materials Engineering Katholieke Universiteit Leuven Kasteelpark Arenberg 44 B‐3001 Belgium University Hasselt and transnational University Limburg BIOMED Diepenbeek Belgium Département de Physique Université de Liège Bât. B5 Allée du 6 août 17 Sart Tilman B‐4000 Belgium Department of Physics Moscow State University 11992 Moscow Russia

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An overlapping Min-Sum LDPC decoder for IEEE 802.11n

An overlapping Min-Sum LDPC decoder for IEEE 802.11n

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18th International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2010

作者： Timakul, Sekson Tanyanon, Itsara Choomchuay, Somsak College of Data Storage Technology and Applications King Mongkut's Institute of Technology Ladkrabang Bangkok 10520 Thailand Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang Bangkok 10520 Thailand

ISBN: (纸本)9781424473717

This paper presents overlapping techniques designed for a compact hardware LDPC decoder with MS algorithm. The design is applicable to IEEE 802.11n standard. We elaborate how to reduce hardware and cycle time between row and column operation. The hardware utilization can be better enhanced and 16-40% cycle time reduction compared to a non-overlapping decoder can be achieved. © 2010 IEEE.

关键词： Decoding

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A design of nonprime block irregular LDPC codes via CRT

A design of nonprime block irregular LDPC codes via CRT

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2010 10th International Symposium on Communications and Information Technologies, ISCIT 2010

作者： Chusin, Chalit Prasartkaew, Chutima Timakul, Sekson Choomchuay, Somsak College of Data Storage Technology and Applications King Mongkut's Institute of Technology Ladkrabang BKK 10520 Thailand Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang BKK 10520 Thailand

ISBN: (纸本)9781424470105

This paper presents a new design of irregular LDPC codes that supports arbitrary block length. We propose the efficient construction method when nonprime size sub-matrices are used. The problem where GCD(L1,L 2) that left unsolved has been tackled. We also consider the case GCD(L1,L2)=1 but L1 or L2 is a nonprime number. The results show that our designed codes have superior performance compared to MAC. The resulted codes still hold the attractive properties of LDPC codes. The performances of interleaved codes are higher than noninterleaved codes and it goes higher as SNR is increased. ©2010 IEEE.

关键词： Codes (symbols)

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An overlapping min-sum LDPC decoder for IEEE 802.11n

An overlapping min-sum LDPC decoder for IEEE 802.11n

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IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)

作者： Sekson Timakul Itsara Tanyanon Somsak Choomchuay College of Data Storage Technology and Applications King Mongkut's Institute of Technology Ladkrabang Bangkok Thailand Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang Bangkok Thailand

关键词： Lead Logic gates Computer architecture Field programmable gate arrays Hardware

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A design of parity check matrix for irregular LDPC codes

A design of parity check matrix for irregular LDPC codes

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2009 9th International Symposium on Communications and Information Technology, ISCIT 2009

作者： Prasartkaew, Chutima Choomchuay, Somsak College of Data Storage Technology and Applications King Mongkut's Institute of Technology Ladkrabang BKK Thailand Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang BKK 10520 Thailand

This paper outlines a work on a design of parity check matrix for Irregular LDPC codes. The design is based on the adjustment of the modified array LDPC codes and interleave-modified array LDPC codes. The code rate of... 详细信息

ISBN: (纸本)9781424445219

关键词： Matrix algebra

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Characterisation of organic field-effect transistors using metal phthalocyanines as active layers

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physica status solidi c 2010年第2期7卷

作者： Iulia G. Korodi Daniel Lehmann Tossapol Tippo Michael Hietschold Dietrich R. T. Zahn Semiconductor Physics Chemnitz University of Technology 09107 Chemnitz Germany Faculty of Engineering and College of Data Storage Technology and Applications King Mongkut's Institute of Technology Ladkrabang Ladkrabang Bangkok 10520 Thailand Solid Surface Analysis Physics Chemnitz University of Technology 09107 Chemnitz Germany

In this work the performance of organic field-effect transistors (OFETs) using Copper Phthalocyanine (CuPc) and Titanyl Phthalocyanine (TiOPc) as active layers is compared. Current/Voltage measurements were first performed in vacuum and later under ambient conditions. The highest hole mobility μ vac = (1.5 ± 0.6) × 10 –3 cm 2 /Vs was obtained for the CuPc OFETs. The mobility remained constant within the error bar after exposing the OFETs to atmosphere ( μ atm = (1.2 ± 0.2) x 10 –3 cm 2 /Vs). For the TiOPc transistors a hole mobility of μ vac = (7.2 ± 4.0) × 10 –5 cm 2 /Vs was found in vacuum. (© 2010 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

关键词： 68.37.Hk 72.80.Le 81.15.Ef 85.30.Tv

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A wideband CMOS variable gain amplifier using active feedback and resistive compensation

A wideband CMOS variable gain amplifier using active feedbac...

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2009 9th International Symposium on Communications and Information Technology, ISCIT 2009

作者： Sakprom, S. Thanachayanont, A. Khumsat, P. Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang Bangkok 10520 Thailand College of Data Storage Technology and Applications King Mongkut's Institute of Technology Ladkrabang Chalongkrung Road Bangkok 10520 Thailand Department of Electrical Engineering Faculty of Engineering Prince of Songkla University Hat-Yai 90112 Thailand

ISBN: (纸本)9781424445219

This paper describes the design and realization of a low power low voltage variable gain amplifier based on an active feedback topology. The proposed amplifier employs the active feedback topology with resistive compensation technique to enhance the operating bandwidth. Simulation results using a 0.18um CMOS technology show that the proposed amplifier can achieve 3.3 GHz bandwidth and 56 dB gain, while drawing 24 mA from a single 1.8-V power supply voltage. ©2009 IEEE.

关键词： Variable gain amplifiers

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A wideband CMOS variable gain amplifier using active feedback and resistive compensation

A wideband CMOS variable gain amplifier using active feedbac...

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International Symposium on Communications and Information Technologies (ISCIT)

作者： S. Sakprom A. Thanachayanont P. Khumsat Faculty of Engineering King Mongkut''s Institute of Technology Ladkrabang Bangkok Thailand Faculty of Engineering and College of Data Storage Technology and Applications King Mongkut''s Institute of Technology Ladkrabang Bangkok Thailand Department of Electrical Engineering Faculty of Engineering Prince of Songkla University Hatyai Thailand

ISBN: (纸本)9781424445219

This paper describes the design and realization of a low power low voltage variable gain amplifier based on an active feedback topology. The proposed amplifier employs the active feedback topology with resistive compensation technique to enhance the operating bandwidth. Simulation results using a 0.18 mum CMOS technology show that the proposed amplifier can achieve 3.3 GHz bandwidth and 56 dB gain, while drawing 24 mA from a single 1.8-V power supply voltage.

关键词： Gain Broadband amplifiers Feedback Bandwidth CMOS technology Voltage Circuits Topology Roentgenium Wideband

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A parity check matrix design for Irregular LDPC codes with 2K block length

A parity check matrix design for Irregular LDPC codes with 2...

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IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)

作者： Chutima Prasartkaew Somsak Choomchuay College of Data Storage Technology and Applications King Mongkut's Institute of Technology Ladkrabang Bangkok Thailand Faculty of Engineering King Mongkut's Institute of Technology Ladkrabang Bangkok Thailand

This paper outlines the work on another design of a parity check matrix for Irregular LDPC codes. The design is based on the pattern of Modified Array and Interleaved Modified Array LDPC codes. The application of matrix transposition Quasi-cyclic shifting has resulted in the reduction of 1's. The designed matrix is suitable for codes with short and medium block lengths. The code rate of 0.56 at the BER of 10 -4 is obtained.

关键词： Parity check codes Bit error rate Memory Block codes Signal design Error correction codes Signal to noise ratio Decoding Signal processing Educational institutions

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