The high complexity of the faulty behavior observed in DRAMs is caused primarily by the presence of internal floating nodes in defective DRAMs. This paper describes a new analysis method to apply electrical simulation...
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The high complexity of the faulty behavior observed in DRAMs is caused primarily by the presence of internal floating nodes in defective DRAMs. This paper describes a new analysis method to apply electrical simulation for investigating the faulty behavior resulting from defects causing two floating nodes within the memory. The paper also presents the results of a simulation study performed on bit line opens to validate the newly proposed method, and suggests a test to detect these bit line opens.
An interesting modeling problem is the need to model one or more of the system modules without exposition to the other system modules. This modeling problem arises due to our interest in these modules or incomplete kn...
An interesting modeling problem is the need to model one or more of the system modules without exposition to the other system modules. This modeling problem arises due to our interest in these modules or incomplete knowledge, or inherent complexity, of the rest of the system modules. Whenever the performance measures (one or more) of the desired modules are available through previous performance studies, data sheets, or previous experimental works, the required performance measures for the whole system can be predicted from our proposed modeling technique. The incomplete knowledge problem of the dynamic behavior of some system modules has been studied by control theory. In the control area, such systems are known as partially observed discrete event dynamic systems, or POS systems. To the best of our knowledge, the performance evaluation of the POS system has not been addressed by the Petri net theory yet. Therefore, in this paper, we propose a new modeling technique for solving this kind of problem based on using the Petri net theory (i.e. Stochastic Reward Nets (SRNs)) in conjunction with the optimal control theory. In this technique, we develop an SRN Equivalent Model (EM) for the modeled system. The SRN EM-model consists of two main nets and their interface nets. One of the main nets represents the part(s) of interest or the known part(s) of the overall POS system that allows us to model its dynamic behavior and evaluate its performance measures. The other main net represents the remaining part(s) of the overall POS system that feeds the part(s) of interest. The well-known maximum principles have been used to develop an algorithm for determining the unknown transition rates of the proposed model. Numerical simulations are given to show that the proposed approach is more effective than the conventional modeling techniques, especially when dealing with systems having a large number of states. Keywords: Discrete event dynamic systems; stochastic reward nets; largen
Stochastic modeling formalisms such as stochastic Petri nets, generalized stochastic Petri nets, and stochastic reward nets can be used to model and evaluate the dynamic behavior of realistic computersystems. Once we...
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Stochastic modeling formalisms such as stochastic Petri nets, generalized stochastic Petri nets, and stochastic reward nets can be used to model and evaluate the dynamic behavior of realistic computersystems. Once we translate the stochastic system model to the underlying corresponding Markov Chain (MC), the developed MC grows wildly to several hundred thousands states. This problem is known as the largeness problem. To tolerate the largeness problem of Markov models, several iterative and direct methods have been proposed in the literature. Although the iterative methods provide a feasible solution for most realistic systems, a major problem appears when these methods fail to reach a solution. Unfortunately, the direct method represents an undesirable numerical technique for tolerating large matrices due to the fill-in problem. In order to solve such problem, in this paper, we develop a Disk-Based Segmentation (DBS) technique based on modifying the Gauss Elimination (GE) technique. The proposed technique has the capability of solving the consequences of the fill-in problem without making assumptions about the underlying structure of the Markov processes of the developed model. The DBS technique splits the matrix into a number of vertical segments and uses the hard disk to store these segments. Using the DBS technique, we can greatly reduce the memory required as compared to that of the GE technique. To minimize the increase in the solution time due to the disk accessing processes, the DBS utilizes a clever management technique for such processes. The effectiveness of the DBS technique has been demonstrated by applying it to a realistic model for the Kanban manufacturing system.
A nonlinear optimization-based identification procedure for fully parameterized multivariable state-space models is presented. The method can be used to identify linear time-invariant, linear parameter-varying, compos...
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Stresses are considered an integral part of any modern industrial DRAM test. This paper describes a novel method to optimize stresses for memory testing, using defect injection and electrical simulation. The new metho...
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Stresses are considered an integral part of any modern industrial DRAM test. This paper describes a novel method to optimize stresses for memory testing, using defect injection and electrical simulation. The new method shows how each stress should be applied to achieve a higher fault coverage of a given rest, based on an understanding of the internal behavior of the memory. In addition, results of a fault analysis study, performed to verify the new optimization method, show its effectiveness.
As a result of variations in the fabrication process, different memory components are produced with different operational characteristics, a situation that complicates the fault analysis process of manufactured memori...
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As a result of variations in the fabrication process, different memory components are produced with different operational characteristics, a situation that complicates the fault analysis process of manufactured memories. This paper discusses the issue of process variations, and shows how to deal with it in the context of fault analysis and test generation. The paper also introduces the concept of border resistance traces as a tool to optimize test stresses and inspect the impact of process variations on the optimization procedure. The concepts are discussed in the paper with the help of a practical example of a specific defect in the memory.
In this paper an intelligent hardware module suitable for the computation of an adaptive median filter (AMF) is presented. The proposed digital hardware structure is pipelined and parallel processing is used to minimi...
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In this paper an intelligent hardware module suitable for the computation of an adaptive median filter (AMF) is presented. The proposed digital hardware structure is pipelined and parallel processing is used to minimize computational time. It is capable of processing gray-scale images of 8-bit resolution with 3/spl times/3 or 5/spl times/5-pixel image neighborhoods as options for the computation of the filter output. However, the system can be easily expanded to accommodate windows of larger sizes. The function of the proposed circuitry is to detect the existence of impulse noise in an image neighborhood and apply the median filter operator only when necessary. Moreover, the noise detection procedure can be customized so that a range of pixel values is considered as impulse noise. In this way, the integrity of edge and detail information of the image under process is preserved and blurring is avoided. The proposed digital structure was implemented in FPGA and it can be used in industrial imaging applications, where fast processing is of the utmost importance. As an example, the time required to perform filtering of a grayscale image of 260/spl times/244 pixels is approximately 7.6 msec. The typical system clock frequency is 65 MHz.
Linked faults are very important for memory testing because they reduce the fault coverage of the tests. Their analysis has proven to be a source for new memory tests, characterized by an increased fault coverage for ...
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Linked faults are very important for memory testing because they reduce the fault coverage of the tests. Their analysis has proven to be a source for new memory tests, characterized by an increased fault coverage for a given test time. This paper presents an analysis of linked faults, based on the concept of fault primitives, such that the whole space of linked faults is investigated, accounted for and validated. The paper also introduces a systematic way to develop tests for such faults.
This paper surveys and investigates the strengths and weaknesses of a number of recent approaches to advanced workflow modelling. Rather than inventing just another workflow language, we briefly describe recent workfl...
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