This paper proposes a reconfigurable processing unit, which performs the MPEG-4 repetitive padding algorithm in real time. The padding unit has been implemented as a scalable systolic structure of processing elements....
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ISBN:
(纸本)1581134622
This paper proposes a reconfigurable processing unit, which performs the MPEG-4 repetitive padding algorithm in real time. The padding unit has been implemented as a scalable systolic structure of processing elements. A generic array of PE has been described in VHDL, and the functionality of the unit has been validated by simulations. In order to determine the chip area and speed of the padding structure, we have synthesized the structure for two FPGA families - Xilinx and Altera. The simulation results indicate that the proposed padding unit can operate in a wide frequency range, depending on the implemented configuration. It is shown that it can process from tens up to hundreds of thousands MPEG-4 macroblocks per second. This allows the real-time requirements of all MPEG-4 profiles and levels to be met efficiently at trivial hardware costs. Finally, the trade-off between chip-area and operating speed is discussed and possible configuration alternatives are proposed. Copyright 2002 ACM.
It has always been assumed that fault models in memories are sufficiently precise for specifying the faulty behavior This means that, given a fault model, it should be possible to construct a test that ensures detecti...
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ISBN:
(纸本)0769514715
It has always been assumed that fault models in memories are sufficiently precise for specifying the faulty behavior This means that, given a fault model, it should be possible to construct a test that ensures detecting the modeled fault. This paper shows that some faults, called partial faults, are particularly difficult to detect. For these faults, more operations are required to complete their fault effect and to ensure detection. The paper also presents fault analysis results, based on defect injection and simulation, where partial faults have been observed. The impact of partial faults on testing is discussed and a test to detect these partial faults is given.
Analyzing the dynamic faulty behavior in DRAMs is a severely time consuming task, because of the exponential growth of the analysis time needed with each memory operation added to the sensitizing operation sequence of...
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Analyzing the dynamic faulty behavior in DRAMs is a severely time consuming task, because of the exponential growth of the analysis time needed with each memory operation added to the sensitizing operation sequence of the fault. In this paper, a new fault analysis approach for DRAM cell defects is presented where the total infinite space of dynamic faulty behavior can be approximated within a limited amount of analysis time. The paper also presents the analysis results for some cell defects using the new approach, in combination with detection conditions that guarantee the detection of any detectable dynamic faults in the defective cell.
The paper proposed a new syntactic annotation scheme - functional chunk, which tried to represent information about grammatical relations between sentence-level predicates and their arguments. Under this scheme, we bu...
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The paper proposed a new syntactic annotation scheme - functional chunk, which tried to represent information about grammatical relations between sentence-level predicates and their arguments. Under this scheme, we built a Chinese chunk bank with about two million Chinese characters, and developed some learned models for automatically annotating fresh text with functional chunks. We also proposed a two-stages approach to build Chinese tree bank on the top of chunk bank, and gave some experimental results of chunk-based syntactic parser to show the advantage of functional chunk for parsing performance increase. All these work lays good foundations for further research project to build a large scale Chinese tree bank.
The ever increasing trend to reduce DPM levels of memories requires tests with very high fault coverage. The important class of dynamic faults, therefore, cannot be ignored any more. It is shown that conventional memo...
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The ever increasing trend to reduce DPM levels of memories requires tests with very high fault coverage. The important class of dynamic faults, therefore, cannot be ignored any more. It is shown that conventional memory tests constructed to detect static faulty behavior of a specific defect do not necessarily detect the dynamic faulty behavior. Indeed, dynamic faulty behavior can take place in the absence of static faults. The paper presents new memory tests derived to target the dynamic fault class.
It has always been assumed that fault modelsin memories are sufficiently precise for specifying the faultybehavior. This means that, given a fault model, it shouldbe possible to construct a test that ensures detecting...
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ISBN:
(纸本)9780769514710
It has always been assumed that fault modelsin memories are sufficiently precise for specifying the faultybehavior. This means that, given a fault model, it shouldbe possible to construct a test that ensures detecting themodeled fault. This paper shows that some faults, calledpartial faults, are particularly difficult to detect. For thesefaults, more operations are required to complete their faulteffect and to ensure detection. The paper also presentsfault analysis results, based on defect injection and simulation,where partial faults have been observed. The impactof partial faults on testing is discussed and a test to detectthese partial faults is given.
In any measuring system the categorization of the error generation factors leads to simplification of complex error problems and to higher suppression of the error. In this paper we categorize, quantify and analyze th...
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The way address sequences and data patterns appear on the outside of a memory may differ from their internal appearance; this effect is referred to as scrambling, which has a large impact on the effectiveness of the u...
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ISBN:
(纸本)0769514537
The way address sequences and data patterns appear on the outside of a memory may differ from their internal appearance; this effect is referred to as scrambling, which has a large impact on the effectiveness of the used tests. This paper presents an analysis of address and data scrambling for memory chips, at the layout and at the electrical level. A method is presented to determine the data backgrounds to be used for the different memory tests. It will be shown that the required data backgrounds are fault model, and hence, also test specific. Industrial results will show the influence of the used data backgrounds on the fault coverage of the tests.
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