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检索条件"机构=Flash Technology Development Team"

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Change of electrical characteristics of a p-type MOSFET via hydrogen effect on boron redistribution

Change of electrical characteristics of a p-type MOSFET via ...

引用

International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

作者： Youngrok Kim Chihak Ahn Alexander Schmidt Joohyun Jeon Sae-Jin Kim Hakseon Kim Hyunjae Kim Hyeyoung Kwon Yero Lee Sung Jin Kim Dongjin Lee Jaeduk Lee Dae Sin Kim Computational Science & Engineering Team Samsung Electronics Hwaseong-si Korea TCAD-Lab Samsung Semiconductor Inc San Jose United States Flash Technology Development Team Samsung Electronics Hwaseong-si Korea

We present a hydrogen-assisted enhanced boron diffusion model in oxide. By introducing the B+OH reaction and BOH diffusion, the model could reproduce the enhanced B diffusion in the presence of high concentrations of hydrogen, which has been reported by previous studies. The model was applied to predict the B profile in the p-type MOSFET and the resulting B profiles were used to predict the threshold voltage (Vth) and the short channel effects (SCE). The simulation results are in good agreement with the measurements. Therefore, the model would be beneficial to optimize the H-involved process conditions.

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Channel Coupling phenomenon as scaling barrier of NAND flash memory beyond 20nm node

Channel Coupling phenomenon as scaling barrier of NAND flash...

引用

IEEE International Memory Workshop (IMW)

作者： ChangHyun Lee Jiyeong Hwang Albert Fayrushin Hyunjung Kim Byoungkeun Son Youngwoo Park Gyoyoung Jin Eunseung Jung Flash Technology Development Team Semiconductor R&D Center Samsung Electronics Company Limited Hwasung Gyeonggi South Korea

A new program disturbance phenomenon appeared from sub 40nm-node NAND flash cell is presented firstly which is named as BTBT Leakage Burst by Channel Coupling (abbr. “Channel Coupling”). With scaling down, the neighboring program channel of 0V grabs strongly the boosted channel at program-inhibited active line not to rise up at the active sidewall and simultaneously, its potential at Si surface is tried to be raised by help of pass voltage. The competition induces the sharp band-bending and thereby sudden enhancement of BTBT leakage, resulting in suppressing channel boosting. In order to overcome “Channel Coupling” appeared at 1X-nm node as a scaling barrier, the air gap in shallow trench isolation is suggested and the effect of the air gap is verified by simulation.

关键词： Electric potential Couplings flash memories Solid modeling Temperature measurement Voltage measurement Atmospheric modeling

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Physical Modeling and Analysis on Improved Endurance Behavior of P-Type Floating Gate NAND flash Memory

Physical Modeling and Analysis on Improved Endurance Behavio...

引用

IEEE International Memory Workshop (IMW)

作者： ChangHyun Lee Albert Fayrushin Sunghoi Hur Youngwoo Park Jungdal Choi Jeonghyuk Choi Chilhee Chung Development Team Semiconductor Research and Development Center Flash Technology Samsung Electronics Company Limited Hwasung Gyeonggi South Korea

In this work, we report improved endurance of p-type floating-gate NAND flash cell. The physical model on the endurance and data retention of p-type floating-gate NAND cells is proposed and the model is verified by using device simulation to elucidate the cause that p-type floating gate has better endurance than n-type floating-gate. The hole currents injected from Si substrate begin to participate in erase operation by using p-type floating gate and the contribution of the holes results in more probable hole-trapping and neutralizing the electron trap in a tunnel oxide with cycling stress. Such hole compensation effect is thought to induce better endurance in p-type floating-gate cell than n-type floating gate cell.

关键词： Electron traps Tunneling Logic gates flash memory Stress Nonvolatile memory

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Inherent Issues and Challenges of Program Disturbance of 3D NAND flash Cell

Inherent Issues and Challenges of Program Disturbance of 3D ...

引用

IEEE International Memory Workshop (IMW)

作者： Keon-Soo Shim Eun-Seok Choi Sung-Wook Jung Se-Hoon Kim Hyun-Seung Yoo Kwang-Sun Jeon Han-Soo Joo Jung-Seok Oh Yoon-Soo Jang Kyung-Jin Park Sang-Moo Choi Sang-Bum Lee Jeong-Deog Koh Ki-Hong Lee Ju-Yeab Lee Sang-Hyun Oh Seung-Ho Pyi Gyu-Seog Cho Sung-Kye Park Jin-Woong Kim Seok-Kiu Lee Sung-Joo Hong Flash Device Technology Team Research and Development Division Hynix Semiconductor Inc. Ichon Gyeonggi South Korea

Program disturbance characteristics of 3D vertical NAND flash cell array architecture have been investigated intensively. A new 'program Y disturbance' mode peculiar to 3D NAND flash cell is defined. Swing characteristics of poly-Si channel and increased NOP (number of program) stress have been compared with 2D planar NAND flash cell. In this paper, new program method pertinent to 3D NAND flash memory was proposed to obtain program disturbance characteristics for MLC.

关键词： Microprocessors Three dimensional displays flash memory DSL Transistors Arrays

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Advanced Hot-Carrier Injection Programming Scheme for Sub 20nm NAND flash Cell and beyond

Advanced Hot-Carrier Injection Programming Scheme for Sub 20...

引用

IEEE International Memory Workshop (IMW)

作者： Sang-Tae Ahn Kyungsik Mun Keun Woo Lee Gyuseog Cho Sung-Kye Park Seokkiu Lee Sungjoo Hong Flash Device Technology Team Research and Development Division Hynix Semiconductor Inc. Ichon Kyunggi South Korea

A novel hot-carrier programming method for 20-nm-node technology NAND flash cell is presented. In order to suppress the program disturb and the large power consumption, we utilized the self-channel boosting techniques with floated WLn-1, switching SSL, and a sufficiently high local field to cause efficient hot-carrier injection in NAND string. This method has been successfully demonstrated in the 20-nm-node NAND flash cells, along with comprehensive studies on various bias conditions and algorithm. It would be very attractive for further scaling in NAND flash memories beyond 20-nm technology.

关键词： Programming Human computer interaction flash memory Hot carrier injection Boosting Switches IEEE Potentials

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Investigation on physical origins of endurance failures in PRAM

Investigation on physical origins of endurance failures in P...

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Annual International Symposium on Reliability Physics

作者： J.S. Bae K.M. Hwang K.H. Park S.B. Jeon J. Choi J.H. Ahn S.S. Kim D.-H. Ahn H.S. Jeong S.W. Nam G.T. Jeong H.K. Cho D.H. Jang C.-G. Park Semiconductor Research and Development Center Samsung Electronics Company Limited Hwaseong South Korea Flash Process Architecture Team Samsung Electronics Company Limited Hwaseong South Korea Materials Science and Engineering Pohang University of Science and Technology Pohang South Korea

Endurance failures are classified into three groups, all of which originate from the atomic transport of GST due to electromigration in molten phase. Based on the analysis, cell structure insusceptible to the atomic t... 详细信息

关键词： Resistance Phase change random access memory Electromigration Computer architecture Probes Tomography Electrodes

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Adaptive two-line inversion driving for low-power display

Adaptive two-line inversion driving for low-power display

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31st International Display Research Conference 2011, EuroDisplay 2011

作者： Choi, Sung-Pil Lee, Myung-Hee Chun, Jung-Hoon Jun, Young-Hyun DDI Development Team SAMSUNG Electronics Yong-In Korea Republic of Sungkyunkwan Univ. Suwon Korea Republic of Flash Product and Technology SAMSUNG Electronics Hwa-Sung Korea Republic of

ISBN: (纸本)9781618396006

New two-line based inversion driving method is introduced for low-power consumption of display driver IC. By separated control between offset cancellation and LCD's polarity, we can decrease power consumption without any degradation of display quality. Experimental results show 12%'s decrease of power consumption in DDI at white pattern and 27% at black pattern with 17'' LCD application.

关键词： Liquid crystal displays

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New Read Scheme of Variable Vpass-Read for Dual Control Gate with Surrounding Floating Gate (DC-SF) NAND flash Cell

New Read Scheme of Variable Vpass-Read for Dual Control Gate...

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IEEE International Memory Workshop (IMW)

作者： HyunSeung Yoo EunSeok Choi HanSoo Joo GyuSeog Cho SungKye Park Seiichi Aritome SeokKiu Lee SungJoo Hong Flash Device Technology Team Research and Development Division Hynix Semiconductor Inc. Icheon South Korea

New read operation scheme has been proposed for three-dimensional (3D) Dual Control gate with Surrounding Floating gate (DC-SF) NAND flash memory [1]. Based on TCAD and analytic model, the selected cell threshold voltage (VT) is increased by high neighbor cell VT because neighbor cell does not have enough Vpass-read to be "pass-transistor" in conventional read operation. To prevent this neighbor cell high VT effect, higher Vpass-read is applied to control gate (CG) of neighbor cell. And lower Vpass-read is applied to CG of the next neighbor cell to compensate FG potential of neighbor cell. For read operation of multi level cell, Vpass-read modulation has to be decreased corresponding to the selected cell read voltage VR. By using new read scheme, a stable read operation is successfully achieved in DC-SF NAND flash cell for MLC (2bit/cell) and TLC (3bit/cell).

关键词： flash memory Analytical models Logic gates Three dimensional displays Transistors Capacitors Nonvolatile memory

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A highly manufacturable integration technology for 27nm 2 and 3bit/cell NAND flash memory

A highly manufacturable integration technology for 27nm 2 an...

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International Electron Devices Meeting (IEDM)

作者： Choong-Ho Lee Suk-Kang Sung Donghoon Jang Sehoon Lee Seungwook Choi Jonghyuk Kim Sejun Park Minsung Song Hyun-Chul Baek Eungjin Ahn Jinhyun Shin Kwangshik Shin Kyunghoon Min Sung-Soon Cho Chang-Jin Kang Jungdal Choi Keonsoo Kim Jeong-Hyuk Choi Kang-Deog Suh Tae-Sung Jung Flash Process Architecture Team Flash Development Center Samsung Electronics Company Limited Hwasung Gyeonggi South Korea Process Development Team Semiconductor Research and Development Center Samsung Electronics Company Limited Hwasung Gyeonggi South Korea Flash Core Technology Laboratory Samsung Electronics Company Limited Hwasung Gyeonggi South Korea Department of Semiconductor systems engineering Sungkyunkwan University Suwon South Korea

A highly manufacturable multi-level NAND flash memory with a 27nm design rule has been successfully developed for the first time. Its unit cell size is 0.00375um 2 (with overhead). Self Aligned Reverse Patterning is used to improve initial Vth distribution induced from DPT (Double Patterning technology) process. By using advanced channel doping technique, the channel junction leakage is minimized and the Vpass window is improved. The optimized doping structure and cell operation scheme are evaluated. And finally 2 and 3bit per cell operation are successfully demonstrated with flash cells of 32Gb density with reasonable reliability.

关键词： flash memory Doping Logic gates Computer architecture Microprocessors Reliability Oxidation

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Highly Reliable Vertical NAND technology with Biconcave Shaped Storage Layer and Leakage Controllable Offset Structure

Highly Reliable Vertical NAND Technology with Biconcave Shap...

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Symposium on VLSI technology

作者： Won-seok Cho Sun Il Shim Jaehoon Jang Hoo-sung Cho Byoung-Koan You Byoung-Keun Son Ki-hyun Kim Jae-Joo Shim Choul-min Park Jin-soo Lim Kyoung-Hoon Kim Ju-Young Lim Hui-Chang Moon Sung-min Hwang Hyun-seok Lim Han-Soo Kim Jungdal Choi Chilhee Chung Flash Core Technology Lab Semiconductor R&D Center Samsung Electronics Co. Ltd.San #24 Nongseo-Dong Giheung-Gu Yongin-City Gyeonggi-Do 449-711 Korea Process Development Team Semiconductor R&D Center Samsung Electronics Co. Ltd.San #24 Nongseo-Dong Giheung-Gu Yongin-City Gyeonggi-Do 449-711 Korea

ISBN: (纸本)9781424454518

The performance and reliability of 3-D NAND cells fabricated by TCAT (Terabit Cell Array Transistor) technology have been improved significantly via a damascened metal gates and a controlled offset between BL contact and select transistor. The damascened metal gate providing sufficiently low resistance is achieved by adopting a novel metal process. Highly suppressed disturbance property-is achieved by the appropriate offset which reduces the leakage current through the select transistor. It is proved that the TCAT NAND is a manufacturable technology in terms of reliability as well as performance in a channel hole with a diameter of 90nm.

关键词： flash memory Vertical 3D TCAT and CTF

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