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检索条件"机构=Flexible 3D System Integration Laboratory"

共 60 条记录，以下是1-10 订阅

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Semiconductor Packaging: Beginning of Sinter Joining and Future

引用

Journal of Japan Institute of Electronics Packaging 2024年第7期27卷 642-649页

作者： Suganuma, Katsuaki Chen, Chuantong Flexible 3D System Integration Laboratory SANKEN Osaka University 8-1 Mihogaoka Ibaraki Osaka567-0047 Japan

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Assessment of Thermal dissipation Ability of Assembled Modules Bonded by Metallic Pastes, Pb-free Solder, and Thermally Conductive Sheet 23

Assessment of Thermal Dissipation Ability of Assembled Modul...

引用

23rd International Conference on Electronics Packaging, ICEP 2024

作者： Hsieh, Ming-Chun Suetake, Aiji Zhang, Zheng Okumura, Rieko Anai, Kei Hattori, Takashi Suganuma, Katsuaki Osaka University Flexible 3D System Integration Laboratory Sanken Osaka567-0047 Japan Saitama362-0021 Japan

ISBN: (纸本)9784991191176

Thermal management measures greatly affect the reliability of electronic devices. A proper thermal management measure enhances the device's lifetime and prevents premature failures. A effective way to optimize thermal dissipation of assembled device is to choose suitable material to bond chip/substrate and substrate/heat sink locations. Innovative materials such as various metallic pastes and thermal interface material (TIM) sheets have been proposed as candidates for bonding. Although these proposed materials have superior thermal conductivities, their thermal dissipation abilities after assembling have not been sufficiently assessed yet. In this study, 5-layer construction samples were prepared as shown in Fig. 1. Cu paste, Ag paste, conventional Pb-free solder, or thermal conductive sheet were used to bond chip/substrate and substrate/heat sink. The temperatures of the chip surface were monitored after a fixed current flowed into the prepared samples for the designated time. As a result, samples that have metal pastes, either Cu and Ag at both chip/substrate and substrate/heat sink, showed low chip surface temperature, which means having high heat dissipation among all prepared samples. © 2024 Japan Institute of Electronics Packaging.

关键词： Sintering

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Reliability Evaluation of SiC/Cu Substrate die-attached Modules with Sintered Cu Joint and Pb-free Solder 22

Reliability Evaluation of SiC/Cu Substrate Die-attached Modu...

引用

22nd International Conference on Electronics Packaging, ICEP 2023

作者： Hsieh, Ming-Chun Suetake, Aiji Zhang, Zheng Okumura, Rieko Anai, Kei Konno, Satoshi Suganuma, Katsuaki Flexible 3D System Integration Laboratory SANKEN Osaka University Osaka567-0047 Japan Saitama362-0021 Japan

ISBN: (纸本)9784991191152

Semiconductor material used in power device gradually shifts from conventional Si to SiC and GaN in order to achieve lower energy loss and higher power-transfer efficiency by taking advantage of the wide bandgap characteristic of new semiconductor materials. The new materials, SiC and GaN enhance power device design to be more size-compacted and enable power devices to endure higher temperature during usage. At the same time, this implies peripheral material needs to endure severer working environment. However, the reliability under harsh environment of joint material that used to connect semiconductor to substrate is not sufficient investigated yet. In order to better understand how joint material, Cu paste and solder, behave in harsh environment, we evaluated thermal reliability of realistic SiC chip with Ag or Au metallization/Cu substrate modules with different die-attaches, that are sintered Cu joint and Pb-free solder joint, by applying long-term thermal cycles. And reliability was investigated by the comparison of nondestructive acoustic tomography images and thermal transient resistance analysis. © 2023 Japan Institute of Electronics Packaging.

关键词： Sintering

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Quantitative Elemental Characterization for Electroless Cu Plating Interface of Micro-via by ToF-SIMS 23

Quantitative Elemental Characterization for Electroless Cu P...

引用

23rd International Conference on Electronics Packaging, ICEP 2024

作者： Nishijima, Masahiko Hsieh, Ming-Chun Zheng, Zhang Okumuara, Rieko Suetake, Aiji Yoshida, Hiroyoshi Chen, Chuantong Seto, Hiroaki Kitahara, Yuhei Hashizume, Kei Suganuma, Katsuaki Osaka University Flexible 3D System Integration Lab Sanken Japan Okuno Chemical Industries Co. Ltd. Japan

ISBN: (纸本)9784991191176

we investigated the electroless Cu plating layer of micro-vias which was prepared by two methods;a widely used (traditional) electroless Cu plating and a newly developed (OPC-FLET). We carried out the elemental characterization for these two electroless Cu plating by the time of flight secondary ions mass spectrometry (ToF-SIMS) and some elements (H, O, C and S)were quantitatively estimated by combustion method. © 2024 Japan Institute of Electronics Packaging.

关键词： Secondary ion mass spectrometry

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development of Thermal Characteristics Evaluation system for Multi-Chip SiC Power Modules 23

Development of Thermal Characteristics Evaluation System for...

引用

23rd International Conference on Electronics Packaging, ICEP 2024

作者： Huo, Fupeng Chen, Chuantong Zhang, Zheng Suetake, Aiji Takeshita, Kazutaka Yamaguchi, Yoshiji Momose, Yashima Suganuma, Katsuaki The Institute Of Science And Industrial Research Osaka University Flexible 3D System Integration Laboratory Osaka565-0871 Japan Yamato Scientific Co. Ltd. Tokyo104-0053 Japan

ISBN: (纸本)9784991191176

With the development trend of high power, high integration, and miniaturization of power electronics, the junction temperature has increased up to 250°C. Moreover, an integrated power module is composed of multiple chips, and its thermal field distribution is more complex than that of a single chip. Therefore, effective thermal analysis and reliability assessment of multi-chip power modules is very important. To solve this problem, our laboratory originally developed a thermal characteristics evaluation system for multi-chip SiC power modules. In this study, the new test platform was proposed. Based on finite element simulation, the thermal interference characteristics between chips were explored. © 2024 Japan Institute of Electronics Packaging.

关键词： Silicon carbide

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Study of Cu Micro-via by TOF-SIMS and STEM 22

Study of Cu Micro-via by TOF-SIMS and STEM

引用

22nd International Conference on Electronics Packaging, ICEP 2023

作者： Nishijima, Masahiko Hsieh, Ming-Chun Zheng, Zhang Suetake, Aiji Yoshida, Hiroshi Okumuara, Rieko Chen, Chuantong Homma, Hidekazu Kita, Koji Suganuma, Katsuaki Osaka University Flexible 3D System Integration Lab SANKEN Japan Okuno Chemical Industries Co. Ltd. Japan

ISBN: (纸本)9784991191152

The micro-via is a sandwiched structure with Cu electrolyte plating/electroless Cu plating/Cu electrolyte plating Pad, and the quality of the electroless Cu layer significantly affects the reliability of micro-via. In this work, we investigated the elemental ingredient of micro-vias which were prepared by a traditional electroless Cu plating method and a newly developed electroless Cu plating method by time of flight secondary ion mass spectrometry (TOF-SIMS) and scanning transmission electron microscopy (STEM). It is found that the concentration of hydrogen, oxygen and several elements exist in the electroless Cu layer prepared by traditional method compared to the new one. These can be a potential risk of nanovoids formation in the electroless Cu layer and decrease the reliability of HdI substrate. © 2023 Japan Institute of Electronics Packaging.

关键词： Electrolytes

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Enhanced reliability for power modules via a new Ag/Si sinter joining strategy

Enhanced reliability for power modules via a new Ag/Si sinte...

引用

作者： Liu, Yang Chen, Chuantong Nakayama, Koji S. Ueshima, Minoru Sakamoto, Takeshi Takuya, Naoe Nishikawa, Hiroshi Suganuma, Katsuaki Flexible 3D System Integration Laboratory Osaka University Osaka Japan Daicel Corporation Osaka Japan Joining and Welding Research Institute Osaka University Osaka Japan

—In this work, with an appropriate adding amount of 20 vol% Si, the novel Ag-Si sintering demonstrated enhanced reliability during thermal shock cycling, specifically including the improved bonding strength stability as well as good microstructure maintenance. The high reliability can be attributed to the reduced CTE value of composited Ag-Si sintering inhibition of thermomechanical stress generation, allowing for the ultra-stable joining structure without coarsening, delamination and deformation. Additionally, the well-adhered interface between sintered Ag and Si additive was also verified by examining the microstructure, ensuring the reliable bonding characteristics of the Ag/Si sintered joint. © 2023 IMAPS-International Microelectronics and Packaging Society. All rights reserved.

关键词： Sintering

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Enhanced Reliability for Power Modules via a New Ag/Si Sinter Joining Strategy 24

Enhanced Reliability for Power Modules via a New Ag/Si Sinte...

引用

24th European Microelectronics and Packaging Conference, EMPC 2023

作者： Liu, Yang Chen, Chuantong Nakayama, Koji S. Ueshima, Minoru Sakamoto, Takeshi Takuya, Naoe Nishikawa, Hiroshi Suganuma, Katsuaki Osaka University Flexible 3D System Integration Laboratory Osaka Japan Daicel Corporation Osaka Japan Joining and Welding Research Institute Osaka University Osaka Japan

ISBN: (纸本)9780956808691

In this work, with an appropriate adding amount of 20 vol % Si, the novel Ag-Si sintering demonstrated enhanced reliability during thermal shock cycling, specifically including the improved bonding strength stability as well as good microstructure maintenance. The high reliability can be attributed to the reduced CTE value of composited Ag-Si sintering inhibition of thermomechanical stress generation, allowing for the ultra-stable joining structure without coarsening, delamination and deformation. Additionally, the well-adhered interface between sintered Ag and Si additive was also verified by examining the microstructure, ensuring the reliable bonding characteristics of the Ag/Si sintered joint. © 2023 IMAPS-Europe.

关键词： Sintering

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20 μm Copper Micro-Bump Bonding Through a Silver Metallization for Advanced Packaging under a Low-Pressure Condition 24

20 μm Copper Micro-Bump Bonding Through a Silver Metallizat...

引用

24th European Microelectronics and Packaging Conference, EMPC 2023

作者： Zhang, Zheng Hsieh, Ming-Chun Suetake, Aiji Yoshida, Hiroshi Okumuara, Rieko Kagami, Noriko Okamoto, Kazamasa Chen, Chuantong Hashizume, Kei Hasegawa, Norihiko Yoshida, Ryuji Homma, Hidekazu Suganuma, Katsuaki Osaka University Flexible 3D System Integration Lab SANKEN 5670047 Japan Okuno Chemical Industries Co. Ltd 5410045 Japan

ISBN: (纸本)9780956808691

In this work, we proposed a copper (Cu) micro-bump bonding strategy by using a silver (Ag) metallization layer as an interconnect bridge. Si chips with 20 μm Cu-Ag bumps were bonded under a low pressure (0.4 MPa) and atmospheric conditions at 250°C. By investigating the surface morphology evolution of the Cu-Ag bump, it is found that severe surface deformation caused by Ag abnormal grain growth and hillock generation plays a critical role in the Cu-Ag bump bonding, which facilitates the approach and bonding of top and bottom Ag surface of the bump structure. Moreover, this bonding strategy is expected to be particularly advantageous for fine-pitch interconnect applications. It not only mitigates the severe bonding condition requirements that are used in thermal compression bonding and hybrid bonding, but also provides higher quality bonding structures for advanced packaging. © 2023 IMAPS-Europe.

关键词： Copper

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Effect of Ni additive on electroless Cu quality for high density interconnect PCB substrate 22

Effect of Ni additive on electroless Cu quality for high den...

引用

22nd International Conference on Electronics Packaging, ICEP 2023

作者： Zhang, Zheng Hsieh, Ming-Chun Nishijima, Masahiko Suetake, Aiji Yoshida, Hiroshi Okumuara, Rieko Chen, Chuantong Homma, Hidekazu Kita, Koji Suganuma, Katsuaki Osaka University Flexible 3D System Integration Lab SANKEN 5670047 Japan Okuno Chemical Industries Co. Ltd 5410045 Japan

ISBN: (纸本)9784991191152

Microvias play a key role in the high density interconnect (HdI) printed circuit board (PCB) substrate, which provides electrical interconnect among build-up layers. To achieve a high quality microvia structure, a flawless electroless Cu seed layer is necessary. In this work, we investigated the nanovoids in the electroless layer caused by hydrogen bubbles and explore the effect of Ni additive on the nanovoid generation. It is found that a high Ni concentration can increase Cu reaction speed and nano-voiding phenomena in terms of size and numbers. This might be due to the high Cu reaction speed leading to the hydrogen bubbles have a few time to escape from the Cu surface and then getting trapped in the deposition layer. © 2023 Japan Institute of Electronics Packaging.

关键词： Substrates

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