The analog part of a high-resolution A/D converter has been integrated in a compatible CMOS-JFET technology. The circuit, which forms a pulse-density modulator (PDM), can be operated at sample rates up to 12 MHz and r...
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The analog part of a high-resolution A/D converter has been integrated in a compatible CMOS-JFET technology. The circuit, which forms a pulse-density modulator (PDM), can be operated at sample rates up to 12 MHz and reaches a peak SNR of 84 dB over a baseband of 20 kHz. This corresponds to approximately 14-bit A/D resolution.
Monolithic analog-to-digital (A/D) and digital-to-analog (D/A) converters suffer from the limited accuracy of the available circuit compensators. A self-calibration method allows the correction of the linearity errors...
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Monolithic analog-to-digital (A/D) and digital-to-analog (D/A) converters suffer from the limited accuracy of the available circuit compensators. A self-calibration method allows the correction of the linearity errors of binary-weighted current-source arrays commonly used in high-speed converters. To achieve high-calibration accuracy a modified dual-slope method is used. This makes it possible to implement A/D and D/A converters with a resolution of 14 b or more at a conversion time of less than 15 mu s.< >
In this communication we discuss the design, merits, and applications of tunable BiCMOS circuits. Although the BiCMOS technology offers higher design flexibility due to the presence of more types of active devices tha...
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In this communication we discuss the design, merits, and applications of tunable BiCMOS circuits. Although the BiCMOS technology offers higher design flexibility due to the presence of more types of active devices than the standard CMOS or bipolar technologies, it is also costlier. Hence, its use can be justified only if the salient features of BiCMOS are taken advantage of adequately. The presented work discusses one possible approach that cannot be easily and economically duplicated in other technologies.
This contribution describes a fully integrated field segment photo sensor for use in single lens reflex cameras. It supplies measurement data from five segments and the integral value via a standard interface io the c...
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This contribution describes a fully integrated field segment photo sensor for use in single lens reflex cameras. It supplies measurement data from five segments and the integral value via a standard interface io the camera processor. Individual calibration data of each sensor is stored In an on-chip EEPROM. The IC has been manufactured in a standard CMOS technology. The sensor operates over more than six decades of illumination to below 1 mlux. It represents an example of complex smart sensor integration.
A DPCM (differential pulse-code modulation) coder integrated in a 2-/spl mu/m CMOS technology is discussed. The motivation was to introduce low-cost coders for video signals compatible with the planned European ISDN. ...
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A DPCM (differential pulse-code modulation) coder integrated in a 2-/spl mu/m CMOS technology is discussed. The motivation was to introduce low-cost coders for video signals compatible with the planned European ISDN. Due to the internal feedback loop, the main problem was to achieve the required operating speed of 13.5 MHz sampling rate. Measurements of fabricated samples proved that the expected performance was achieved.
In this paper, we present a 16/spl times/16 analog vector-matrix multiplier with analog electrically erasable and programmable read-only memories (EEPROMs) used as nonvolatile storage for the weight matrix values. Eac...
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In this paper, we present a 16/spl times/16 analog vector-matrix multiplier with analog electrically erasable and programmable read-only memories (EEPROMs) used as nonvolatile storage for the weight matrix values. Each weight matrix value is stored in an EEPROM transistor as a change of the threshold voltage, and the same EEPROM transistor is used for the multiplication by utilizing the square-law characteristic of the metal-oxide-semiconductor field-effect transistor. This allows a very simple circuit for the multiplier array with a size of about 1/spl times/1 mm/sup 2/. The vector-matrix multiplier has been fabricated in a 1,5-/spl mu/m single-poly complementary metal-oxide-semiconductor/EEPROM technology and successfully tested.
This paper investigates the feasibility of realization of analog microwave circuits in submicron CMOS technologies, particularly in bulk-CMOS and CMOS/SIMOX. The investigation concentrates on implementation of wideban...
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This paper investigates the feasibility of realization of analog microwave circuits in submicron CMOS technologies, particularly in bulk-CMOS and CMOS/SIMOX. The investigation concentrates on implementation of wideband amplifiers operating from DC to RF frequencies in the GHz range at power supplies /spl les/5 V.
The channel selection in direct-downconversion receivers can be performed using analog or digital filters or a combination of both. For an appropriate partitioning in early design phase knowledge about the power-perfo...
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The channel selection in direct-downconversion receivers can be performed using analog or digital filters or a combination of both. For an appropriate partitioning in early design phase knowledge about the power-performance tradeoffs of the building blocks is necessary without knowledge about too many implementation details. This paper proposes a method to carry out the noise-power trade-off of analog G m -C filters. For a particular example where the demand on adjacent channel rejection is very high it is shown that the analog solution is very promising when compared to the digital channel selection
An adaptive filter for computation of the Gabor transformation of images is presented. The filter design is based on the LMS algorithm for complex signals. A significant simplification of the filter structure and the ...
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An adaptive filter for computation of the Gabor transformation of images is presented. The filter design is based on the LMS algorithm for complex signals. A significant simplification of the filter structure and the use of FFT algorithms lead to a very fast and efficient computation of the coefficients when compared with known algorithms. Further, computer simulations indicate that sufficient precision and a fast convergence of the coefficients can be obtained.< >
This paper describes a highly flexible design rule independent ROM generator for BiCMOS technology with full CAD support for compilation, verification, simulation, and documentation. The flexibility is mainly achieved...
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This paper describes a highly flexible design rule independent ROM generator for BiCMOS technology with full CAD support for compilation, verification, simulation, and documentation. The flexibility is mainly achieved by a quantization of the memory space by steps of only one word and by the option of an arbitrary aspect ratio of the ROM matrix. Special BiCMOS circuits have been developed for speed optimization and integrated in the CAD tool. An overview on the design flow is given.
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