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Optics Continuum 2025年第4期4卷 789-803页

作者： Esteban Farfán-Guillén, David Camporez, Higor Silva, Jair Adriano Lima Castellano Rodriguez, Juan Camilo Pohl, Alexandre De Almeida Prado CPGEI–Graduate Program in Electrical Engineering and Computer Science Federal University of Technology Paraná Curitiba80230–901 Brazil Graduate Program in Electrical Engineering Federal University of Espírito Santo Vitória29075-960 Brazil

Visible light communications (VLC) enable wireless data transmission using existing light-emitting diode (LED) illumination. This experimental study evaluates the performance of multiple input and multiple output (MIMO) configurations in indoor VLC systems by analyzing their impact on both communication and illumination. Various MIMO setups (2 × 2, 3 × 2, and 4 × 2) are compared against single input single output (SISO), and single input multiple outputs (SIMO) schemes, using commercial LED luminaires as transmitters. While the 4 × 2 MIMO configuration demonstrates superior overall performance, intermediate configurations like 3 × 2 or 2 × 2 MIMO offer an attractive trade-off between system complexity and performance enhancement, particularly in scenarios with space or cost constraints. The results show that MIMO configurations significantly outperform SISO systems, achieving reliable communication (BER ≤ 10−3) at practical indoor distances of up to 2 meters while maintaining illumination levels above 300 lux, where conventional SISO setups do not meet these dual requirements. These findings demonstrate the practical feasibility of MIMO-VLC systems for indoor deployments. © 2025 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement.

关键词： Frequency division multiplexing Modulation techniques Multiple input multiple output Quadrature amplitude modulation Signal processing Visible light communications

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FPGA implementation of low cost and low power chaotic encryption scheme based on a discrete-space chaotic map

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Multimedia Tools and Applications 2025年 1-22页

作者： Moreira Bezerra, João Inácio Machado, Gustavo Iankowski Soares, Rafael Valduga de Almeida Camargo, Vinícius Molter, Alexandre Post Graduate Program in Computer Science Universidade Federal de Pelotas Rio Grande do Sul Pelotas96010610 Brazil Graduate Program in Computer Engineering Universidade Federal de Pelotas Rio Grande do Sul Pelotas96010610 Brazil Post Graduate Program in Mathematical Modeling Universidade Federal de Pelotas Rio Grande do Sul Capão do Leão96160000 Brazil

The exponential growth of the number of devices connected to the Internet and the use of IoT applications increases the amount of data exchange over public channels in low-cost and low-power embedded systems. Images are the most widely shared files, and standard symmetric algorithms such as the Advanced Encryption Standard (AES) are optimized for text but not image encryption. Consequently, new approaches like chaotic encryption have attracted researchers’ interest. Chaotic encryption schemes have been analyzed mostly from a software standpoint, but recent advancements in the field, through the use of discrete chaotic maps, enabled the development of simpler hardware implementations of ciphers with promising reductions in power and cost and increased performance. This work presents the Field-programmable Gate Array (FPGA) implementation of a simultaneous permutation-diffusion chaotic encryption scheme utilizing a discrete-space chaotic map. The FPGA implementation of the cipher is analyzed considering area, maximum frequency, and power consumption, and comparisons are made with the AES. The proposed algorithm has a satisfactory trade-off between area, power and performance, obtaining a peak throughput 59% higher than state-of-the-art symmetric ciphers in the literature. Thus, the proposed cipher shows that chaotic ciphers are viable for both high-performance and low-power embedded devices. Tests verified the security of the proposed cipher against statistical, differential, brute-force, and chosen plain-text attacks. © The Author(s), under exclusive licence to Springer science+Business Media, LLC, part of Springer Nature 2025.

关键词： Cryptography

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TaxDiff: taxonomic-guided diffusion model for protein sequence generation

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science China(Information sciences) 2025年第4期68卷 385-386页

作者： Zongying LIN Hao LI Liuzhenghao LV Yu WANG Bin LIN Junwu ZHANG Zijun CHEN Calvin Yu-Chian CHEN Li YUAN Yonghong TIAN School of Electronic and Computer Engineering Peking University AI for Science (AI4S)-Preferred Program Peking University Shenzhen Graduate School Peng Cheng Laboratory School of Chemical Biology and Biotechnology Peking University

Protein design aims to generate protein variants with targeted biological functions, which is significant in multiple biological areas, including enzyme reaction catalysis, vaccine design, and fluorescence intensity. Protein design contains two paradigms: sequence generation and structure generation. Recently, EvoDiff [1] proposed a universal designing paradigm, combining structure and sequence generation using the diffusion framework, which improves the protein design efficiency.

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An Extended Euclidean Algorithm Implementation over Ciphertext Space 2nd

An Extended Euclidean Algorithm Implementation over Ciphert...

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2nd International Conference on Security and Information Technologies with AI, Internet Computing and Big-data Applications, SITAIBA 2023

作者： Chi, Po-Wen Lin, Yuan-Pang Wang, Ming-Hung Chuang, Yun-Hsin Department of Computer Science and Information Engineering National Taiwan Normal University Taiwan Taipei Taiwan Department of Computer Science and Information Engineering National Chung Cheng University Taiwan Chiayi Taiwan Engineering Management Graduate Program College of Engineering National Cheng Kung University Taiwan Tainan Taiwan

ISBN: (纸本)9789819777853

Fully homomorphic encryption (FHE) is a useful cryptographic primitive. It makes a third-party manipulate data in the ciphertext space and therefore is a key technology for privacy-preserving outsourcing services. Theoretically, FHE can evaluate any circuits. However, the implementation is not trivial. The reason it lacks lots of basic operations like conditional check and branch control. In this paper, we focus on extended Euclidean algorithm operation over FHE. We introduce the problems we encounter and show how we solve these issues. We implement our design and evaluate its performance on a real computer. Finally, we propose some research directions for our future work. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： Ciphertext

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The Effect of WebRTC Jitter Buffer on Cloud Streaming Game QoE

The Effect of WebRTC Jitter Buffer on Cloud Streaming Game Q...

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Consumer Technology (ICCT-Pacific), International Conference on

作者： Naoyasu Kaneko Toshiro Nunome Department of Engineering Computer Science Program Graduate School of Engineering Nagoya Institute of Technology Nagoya Japan

ISBN: (数字)9798331504120

ISBN: (纸本)9798331504137

This paper considers a cloud streaming game using WebRTC. Since the cloud streaming game consists of a server and a client, the network quality between them affects the game. Among the network quality degradation factors, we focus on delay jitter. We reduce the effect of the jitter by buffering. We conduct a subjective experiment of a single-player action game and evaluate application-level QoS and QoE. We investigate the impact of buffering on the video and audio quality of the user playing the game.

关键词： Degradation Games Quality of service Jitter Streaming media Cloud gaming Delays Quality of experience Servers WebRTC

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A Design Study on Integrated Complex Coefficient Filters with Peripheral Circuits for Accurate Frequency Response Measurement

IEEJ Transactions on Electronics, Information and Systems

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IEEJ Transactions on Electronics, Information and Systems 2025年第1期145卷 16-24页

作者： Shouno, Kazuhiro Sato, Lina Fukagawa, Kanta Tanimoto, Hiroshi Muto, Cosy Division of Information Engineering University of Tsukuba 1-1-1 Tennoudai Ibaraki Tsukuba305-8573 Japan Graduate School of Science and Technology Degree Programs in Systems and Information Engineering Master’s Program in Computer Science University of Tsukuba Japan Kitami Institute of Technology 165 Koen-cho Hokkaido Kitami090-8507 Japan Faculty of Education Nagasaki University 1-14 Bunkyo-machi Nagasaki852-8521 Japan

This paper proposes a measurement technique for an integrated complex filter. The proposed method is based on two measurement methods with integrated circuitry for calibration. It is accomplished by applying square waves to an FUT (Filter Under Test) instead of sinusoidal waves or by superposing transfer characteristics obtained by applying a single sinusoidal wave to an FUT. In both of the above methods, the output signal connected to the external measurement equipment via a 50 Ω coaxial cable and so on. In this case, the output signal of the FUT should be amplified by internal or external amplifiers, which degrades the response. However, it is cancelled out by the proposed calibration circuitry with some analog switches. In addition to the above, for the RC polyphase filter, the source resistance and the load capacitance degrade the measurement results and their effect is discussed. The validity of the proposal is confirmed through computer simulation for a third-order RCPF whose passband is 8–40 MHz fabricated by Phenitec 0.6 µm CMOS process. It is shown that the measurement error is −1.10 dB for the square-wave method and −1.00 dB and −0.43 degrees for the superposition method at 40 MHz. © 2025 The Institute of Electrical Engineers of Japan.

关键词： Capacitance

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Damage-Free Neutral Beam Etching for Gate Recess in E-Mode AlGaN/GaN HEMTs

IEEE Electron Device Letters

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IEEE Electron Device Letters 2025年第5期46卷 705-708页

作者： Chen, Yi-Ho Chu, Fu-Chuan Aslam, Muhammad Lee, Yao-Jen Li, Yiming Samukawa, Seiji National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Graduate Degree Program of College of Electrical and Computer Engineering Hsinchu300093 Taiwan National Chung-Shan Institute of Science and Technology Solid State Devices Section Electronic System Research Division Taoyuan325 Taiwan National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Electrical Engineering and Computer Science International Graduate Program Hsinchu300093 Taiwan Institute of Pioneer Semiconductor Innovation National Yang Ming Chiao Tung University Hsinchu300093 Taiwan Institute of Pioneer Semiconductor Innovation Institute of Artificial Intelligence Innovation National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Institute of Biomedical Engineering Department of Electronics and Electrical Engineering Institute of Communications Engineering Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Institute of Communications Engineering Department of Electronics and Electrical Engineering Hsinchu300093 Taiwan

Recess gate etching is a critical technique for achieving enhancement-mode (E-mode) AlGaN/GaN high-electron mobility transistors (HEMTs) because the interface is susceptible to the etching damage. This study fabricates recess gates using the neutral beam etching (NBE) technique. By adjusting the aperture thickness in the NBE apparatus, we simulate both NB-mode and plasma-mode etching. The electrical characteristics of E-mode HEMTs fabricated using these two modes are analyzed and compared through DC, noise, and pulsed IV measurements. The results demonstrate that NB-recessed HEMTs exhibit superior performance. © 1980-2012 IEEE.

关键词： Aluminum gallium nitride

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Overlapped Error Correction Codes in Two-Dimensional Structures

Overlapped Error Correction Codes in Two-Dimensional Structu...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Andrew Fritsch Wagner Savaris Adahil Muniz Giovanna Borba Rodrigo Girardi Jarbas Silveira César Marcon Graduate Program in Computer Science (PPGCC) Pontifical Catholic University of Rio Grande do Sul (PUCRS) Brazil Graduate Program in Teleinformatics Engineering (PPGETI) Federal University of Ceará (UFC) Brazil

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

The continuous advancement of communication systems necessitates the development of algorithms capable of identifying and correcting errors that may arise during data transmission and storage. This pursuit of reliability is particularly crucial in critical systems and sectors that are challenging to access, such as space exploration, passenger transportation, and financial services. In this context, the Error Correction Code (ECC) is a fundamental tool for providing a certain degree of reliability to these systems. This research proposes a novel technique to enhance the error correction capacity of ECCs by leveraging region overlapping. Specifically, we propose correcting data areas protected by more than one ECC, which allows for the inference of logical correlations between ECCs, thereby augmenting their error detection and correction capability. Our focus is bidimensional codeword structures, commonly known as 2D-ECCs, which entail a hierarchical arrangement of ECCs. We evaluated the ECC proposal, comparing its error correction and detection capabilities. Through this evaluation, we aim to demonstrate the technique's efficacy in bolstering the reliability and resilience of communication systems, particularly in critical domains where precision and accuracy are paramount.

关键词： Fault tolerance Fault tolerant systems Transportation Error correction codes Error correction Space exploration Proposals Integrated circuit reliability Financial services Resilience

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Data-Driven Incentive Mechanisms for Federated Learning in Vehicular Networks

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IEEE Transactions on Vehicular Technology 2025年

作者： Fathi, Faeze Montazeri, Mina N.araabi, Babak Du, Hongyang Niyato, Dusit Kebriaei, Hamed University of Tehran School of Ece College of Engineering Tehran Iran Urban Energy Systems Laboratory Dübendorf8600 Switzerland Nanyang Technological University School of Computer Science and Engineering The Energy Research Institute @ Ntu Interdisciplinary Graduate Program Singapore Nanyang Technological University School of Computer Science and Engineering Singapore School of Computer Science Tehran Iran

Centralized machine learning algorithms in vehicular networks face privacy and resource constraints. Federated Learning (FL) addresses these by enabling collaborative model training without sharing raw data. To incentivize vehicle participation despite resource constraints, we propose a contract between Roadside Units (RSUs) and vehicles, specifying required computation resources and rewards based on local data quality. The contract is designed to maximize the utility of the RSU, subject to constraints that ensure the participation of the vehicles in the task and truthful reporting of their data quality parameter. However, designing an optimal contract with classical methods is limited to specific utility functions. To extend the design methodology of optimal contracts to a broader range of utility functions, our study proposes a deep learning-based solution. Specifically, we present a novel application of Deep Neural Networks (DNNs), marking the first instance of applying DNNs in contract theory-based incentive mechanisms to achieve nearoptimal contracts. We design the DNN's structure to inherently satisfy specific constraints of the optimization problem, enhancing its efficiency and accuracy in determining the optimal contract. We utilize an augmented Lagrangian method to approximate the optimal contract in federated learning tasks. A case study on traffic sign recognition demonstrates the applicability and effectiveness of our method. Comparing our approach with the well-known generative diffusion model shows that in the FL scenarios, the DNN results are closer to the optimal contract compared to those of the generative diffusion model. © 1967-2012 IEEE.

关键词： Traffic signs

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Testing Facility Location with Constrained Queue Time Problem: A Case Study in Florida, USA 24

Testing Facility Location with Constrained Queue Time Proble...

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Proceedings of the Winter Simulation Conference

作者： Almir Antonio Monteiro Junior Rafael Schneider Vanessa de Almeida Guimarães Pedro Henrique González System Engineering and Computer Science Program Federal University of Rio de Janeiro BRAZIL COPPEAD Graduate School of Business Federal University of Rio de Janeiro BRAZIL

ISBN: (纸本)9798331534202

This study addresses the Testing Facility Location with Constrained Queue Time Problem. This optimization problem focuses on determining the best places to deploy testing sites and their available testers for infectious diseases, while constraining the maximum time in the queue with a given probability. An integer programming model is introduced and applied to the three biggest counties, in terms of population, of Florida, United States. Moreover, the Monte Carlo method is used to evaluate the model's output, aiming to check if the queueing time constraint is being satisfied. Through the experiments, a testing facility deployment plan can be determined for each county and further validated by the simulation. The results show that the solutions returned by the model behaved successfully when submitted to the Monte Carlo method, not exceeding the time in the queue in more than the predefined probability.

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