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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Leonardo Antonietti Morgana Da Rosa Rodrigo Lopes Eduardo Da Costa Rafael Soares Graduate Program on Computing - Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9798350377200

ISBN: (纸本)9798350377217

Multipliers are pivotal in numerous applications, including digital signal processing, image processing, and video processing. Nonetheless, their operation substantially increases power consumption for these applications. Therefore, applying strategies that can reduce power in this arithmetic operator is paramount. This paper presents a novel approach to optimize arithmetic units, focusing on multiplier units, through the integration of the Radix- $2^{m}$ squarer unit (RSU) and 4–2 adder/subtractor compressor (AC). Compared to the state-of-the-art, the proposed multiplier unit, termed MRSU (multiplier unit RSU-based), offers significant area-and energy-savings. The synthesis results show remarkable improvements in the MRSU Dadda 4–2 architecture, which achieves 14.35× more energy-savings for 8 bits, 4.87× for 16 bits, and 2.22× for 32 bits compared to the multiplier unit automatically selected by the logic-synthesis tool. Furthermore, compared to the Booth multiplier with the Dadda compression tree, MRSU Dadda 4–2 exhibits 1.67× more energy-savings for 8 bits, 1.93× for 16 bits, and 1.95× for 32 bits.

关键词： Image coding Power demand Focusing Digital signal processing Computer architecture Very large scale integration Energy efficiency Electronic circuits Adders Arithmetic

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Model Prediction Using Random Forest Algorithm and Time Series Analysis Parts Distribution with in Indonesia Automotive Industry 8

Model Prediction Using Random Forest Algorithm and Time Seri...

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8th International Conference on Informatics and computing, ICIC 2023

作者： Andy Achmad, H. Ramadhan, Arief Warnars Harco Leslie, H. Budiharto, Widodo Bina Nusantara University BINUS Graduate Program Computer Science Computer Science Department Jakarta11480 Indonesia Telkom University School of Computing Bandung40257 Indonesia

ISBN: (纸本)9798350342604

Car spare parts are parts of a car that consist of components that form a certain unity and function, there are some parts that are damaged more often and therefore must be replaced more often. In this research, to predict the availability of spare parts using the times series moving average prediction method with random forest. The dataset used in this research is 19,068 consisting of location, transaction number, transaction date, part number, quantity and odo-km. Distribution of spare parts classified based on recapitulation of spare part distribution is RAE=54.5541% and RSE=63.8888%, distribution of spare parts based on location is RAE=55.5541% and RSE=65.2118%, maintenance based on ODO-KM is RAE=33.0949% and RSE=41.2241 % and distribution quantity RAE=33.749% and RSE=36.2317%. The results of spare part distribution analysis using the Confusion Matrix with probability accuracy are TP Rate=0.903, FP Rate=0.067, Precision=0.911, Recall=0.903, F-Measure=0.893, MCC=0.857, ROC Area=0.983 and PRC Area=0.948. The aim of this research is to determine the factors needed to build a machine learning-based spare parts distribution model, implementation, measurement and prediction in the automotive industry in Indonesia. © 2023 IEEE.

关键词： Automotive industry

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CompressedMediQ: Hybrid Quantum Machine Learning Pipeline for High-Dimensional Neuroimaging Data

CompressedMediQ: Hybrid Quantum Machine Learning Pipeline fo...

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Acoustics, Speech, and Signal Processing Workshops (ICASSPW), IEEE International Conference on

作者： Kuan-Cheng Chen Yi-Tien Li Tai-Yu Li Chen-Yu Liu Po-Heng Henry Lee Cheng-Yu Chen Department of Electrical and Electronic Engineering Imperial College London London UK Centre for Quantum Engineering Science and Technology (QuEST) Imperial College London London UK Translational Imaging Research Center Taipei Medical University Hospital Taipei Taiwan Research Center for Neuroscience Taipei Medical University Taipei Taiwan Ph.D. Program in Medical Neuroscience College of Medical Science and Technology Taipei Medical University Taipei Taiwan National Center for High-Performance Computing NARlabs Hsinchu Taiwan Graduate Institute of Applied Physics National Taiwan University Taipei Taiwan Department of Medical Imaging Taipei Medical University Hospital Taipei Taiwan Department of Radiology National Defense Medical Center Taipei Taiwan Department of Radiology School of Medicine College of Medicine Taipei Taiwan

ISBN: (数字)9798331519315

ISBN: (纸本)9798331519322

This paper introduces CompressedMediQ, a novel hybrid quantum-classical machine learning pipeline specifically developed to address the computational challenges associated with high-dimensional multi-class neuroimaging data analysis. Standard neuroimaging datasets, such as large-scale MRI data from the Alzheimer’s Disease Neuroimaging Initiative and Neuroimaging in Frontotemporal Dementia, present significant hurdles due to their vast size and complexity. CompressedMediQ integrates classical HPC nodes for advanced MRI pre-processing and Convolutional Neural Network (CNN)-PCA-based feature extraction and reduction, addressing the limited-qubit availability for quantum data encoding in the NISQ era. This is followed by Quantum Support Vector Machine (QSVM) classification. By utilizing quantum kernel methods, the pipeline optimizes feature mapping and classification, enhancing data separability and outperforming traditional neuroimaging analysis techniques. Experimental results highlight the pipeline’s superior accuracy in dementia staging, validating the practical use of quantum machine learning in clinical diagnostics. Despite the limitations of NISQ devices, this proof-of-concept demonstrates the transformative potential of quantum-enhanced learning, paving the way for scalable and precise diagnostic tools in healthcare and signal processing.

关键词： Neuroimaging Support vector machines Quantum computing Accuracy Magnetic resonance imaging Pipelines Machine learning Medical services Signal processing Standards

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Exploring Approximate Adders for an Energy-Efficient Pre-Processing Pan-Tompkins Algorithm VLSI Design

Exploring Approximate Adders for an Energy-Efficient Pre-Pro...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Léo Ribeiro Morgana M. A. Rosa Rafael Soares Eduardo Costa Graduate Program on Computing Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9798350391695

ISBN: (纸本)9798350391701

This work explores a set of approximate adders (COPY adder, error-tolerant adder - ETA, lower-part OR adder - LOA, truncation - Trunc, and approximate parallel prefix adder - AxPPA) to enhance a VLSI design for ECG signal preprocessing based on Pan-Tompkins algorithm (AxPTA) to improve energy efficiency and QRS complex detection. Validation with the MIT-BIH database confirms that the AxPTA design maintains excellent sensitivity and positive predictivity with reduced energy consumption and circuit area. The AxPTA with AxPPA achieves a 10.22% reduction in circuit size and saves 85.06% energy, with an acceptable 1.32% precision deviation. These results suggest that the AxPPA significantly boosts energy efficiency in the AxPTA design for ECG analysis, supporting the development of portable devices for continuous heart monitoring and cardiovascular disease prevention.

关键词： Energy consumption Sensitivity Databases Energy conservation Electrocardiography Very large scale integration Approximation algorithms Energy efficiency Adders System analysis and design

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AxMOD: VLSI Modular Reduction Design Exploring Approximate Arithmetic Units

AxMOD: VLSI Modular Reduction Design Exploring Approximate A...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Lourenço Mulling Morgana M. A. Rosa Rafael Soares Eduardo Costa Graduate Program on Computing Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9798350391695

ISBN: (纸本)9798350391701

This work investigates the design of approximate arithmetic operator units used in the VLSI modular reduction (AxMOD) architecture. The AxMOD architecture herein proposed explores the following arithmetic operators: i) two approximate iterative-based fixed-point and Goldschmidt (GLD) dividers, ii) five approximate adders (AxA): COPY adder, error-tolerant adder (ETA), lower-part OR adder (LOA), truncation (Trunc), and approximate parallel prefix adder (AxPPA), and iii) five approximate multipliers of approximate radix-4 multiplier units (AxRMU), dynamic range unbiased multiplier (DRUM), rounding-based approximate (RoBA), truncated multiplier (Trunc), and the leading one-bit based approximate (LoBA). Our demonstration of AxMOD’s efficiency using approximate arithmetic operators from the Pareto-optimal front illustrates the area and power-quality trade-off. Our results reveal that in fixed-point arithmetic, AxRMU with K = 16 and Trunc adder with K = 8 deliver energy savings of up to 4.14× compared to the state-of-the-art.

关键词： Energy consumption Accuracy Energy conservation Power quality Very large scale integration Dynamic range Adders System analysis and design Fixed-point arithmetic

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Evaluating the Resilience of the Approximate Parallel Prefix Adder (AxPPA) Against Hardware Trojan Horse Injection

Evaluating the Resilience of the Approximate Parallel Prefix...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Eloisa Barros Morgana M. A. Rosa Rodrigo Lopes Leonardo Antonietti Eduardo Costa Rafael Soares Graduate Program on Computing Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9798350391695

ISBN: (纸本)9798350391701

Approximate computing (AxC) offers opportunities to enhance computing efficiency by exploiting inherent error resilience. This study examines the security implications of AxC, focusing on adders, where Hardware Trojan Horses (HTH) present significant risks. We propose a framework to inject HTH into approximate adders (AxAs), specifically the Approximate Parallel Prefix Adder (AxPPA), and assess their impact. The framework, implemented in MATLAB (code available at ***/MorganaMacedo/AxPPA_HTH), evaluates HTH injection into AxAs, analyzing error metrics (SSIM, NCC, MSE, MAE, and error-probability) and conducting logic-synthesis (LS) analysis to detect physical anomalies indicative of HTH presence. Our results demonstrate AxPPA’s resilience against HTH injection, with detection thresholds varying with approximation bit size. LS analysis shows AxPPA effectively detects HTHs across all bit approximations, outperforming LOA, particularly at K=16. AxPPA also achieves superior energy savings of 31.95% compared to LOA and notable area savings, highlighting its efficacy in HTH detection and performance optimization.

关键词： Measurement Hardware Trojan horses Security MATLAB Adders System analysis and design Optimization Resilience Testing

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M-AxPPA: An Accurate and Energy-Efficient Modified Approximate Parallel Prefix Adder

M-AxPPA: An Accurate and Energy-Efficient Modified Approxima...

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Rodrigo Lopes Morgana da Rosa Eduardo da Costa Rafael Soares Graduate Program on Computing - Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9798350377200

ISBN: (纸本)9798350377217

This work introduces a combined version of approximate adders (AxAs), joining approximate parallel prefix adders (AxPPA) with other AxAs from the literature (COPY, Truncation - TRUNC, and lower-part OR adder - LOA). We call this approach M-AxPPA (modified approximate parallel prefix adder) and investigate three specific versions: M-AxPPA-COPY, M-AxPPA-TRUNC, and M-AxPPA-LOA. We evaluate 315 different configurations, comparing our novel M-AxPPA to other AxAs proposed in the literature. We present pseudocode examples and investigate the accuracy quality, incorporating metrics like SSIM, NCC, MAE, MRE, and MRED. Additionally, we perform a trade-off analysis between accuracy quality and logic synthesis outcomes, underscoring the advantages of our M-AxPPA, notably the outstanding accuracy achieved by M-AxPPA-LOA (approaching 100%), with a substantial energy-saving.

关键词： Measurement Accuracy Energy efficiency Logic Adders Electronic circuits

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Hardware Design for the Affine Motion Compensation of the VVC Standard

Hardware Design for the Affine Motion Compensation of the VV...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Marcello M. Muñoz Denis Maass Murilo Perleberg Luciano Agostini Marcelo Porto Graduate Program in Computing Federal University of Pelotas Pelotas Brazil

The Affine Motion Estimation (AME) of the Versatile Video Coding (VVC) standard is a high-complexity task. The AME requires Affine Motion Compensation (MC) to be performed for $4\times 4$ subblocks, where the Motion Vector relative to the $4\times 4$ subblock is adopted to define which of the 15 6-tap interpolation filters should be used to interpolate each sample of the $4\times 4$ subblock. This work presents a dedicated hardware implementation for the Affine MC of the VVC standard, where the ASIC synthesis results for this architecture for TSMC 40nm standard cells show an area requirement of 97.5k gates and power dissipation of 11.1mW when targeting the processing of 4K Ultra-High Definition (UHD) video at a frequency of 808MHz. To the best of the author's knowledge, this work presents the first hardware implementation of the VVC Affine MC in the literature.

关键词： Video coding VHDL Motion estimation Logic gates Parallel processing Hardware Motion compensation

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4K UHD@60fps Design For The VVC Affine Motion Estimation Reconstructor

4K UHD@60fps Design For The VVC Affine Motion Estimation Rec...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Marcello M. Muñoz Denis Maass Murilo Perleberg Luciano Agostini Guilherme Correa Marcelo Porto Graduate Program in Computing Federal University of Pelotas Pelotas Brazil

The Versatile Video Coding (VVC) standard adopts the Affine Motion Estimation (AME) as one of its main novelties, which significantly contributed to the coding efficiency gains of VVC over previous standards. On the other hand, AME requires a very high computational effort for processing high-resolution videos in real-time, making dedicated hardware mandatory for battery-powered devices. Considering this scenario, this work presents a dedicated hardware design for the Affine Reconstructor of the VVC standard targeting an ASIC TSMC 40nm standard-cell technology. The synthesis results show 94.4k Gates of area requirements, with 15.36 mW of power dissipation when targeting the processing of 60 fps of 4K Ultra-High Definition (UHD) videos. To the best of the author's knowledge, the presented design is the first in the literature targeting the Affine Reconstructor of the VVC standard.

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Peer Review in Education: Promoting Collaboration, Written Expression, Critical Thinking, and Professional Responsibility

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Education and Information Technologies 2003年第1期8卷 37-46页

作者： Kern, Vinícius Medina Saraiva, Luciana Martins dos Santos Pacheco, Roberto Carlos Computing Science and Engineering and UFSC Graduate Program in Production Engineering UNIVALI at São José Brazil Psychology and UFSC Graduate Program in Production Engineering UNIVALI at Biguaçu Brrazil UFSC Graduate Program in Production Engineering Brazil

This article discusses the application of the peer review process as a pedagogical instrument for the promotion of written expression, collaborative work, critical thinking, and professional responsibility among Informatics and Engineering majors. The approach is introduced with a motivation, followed by a discussion about common principles of current learning paradigms and the peer review process. This work is being conducted in Brazil, where we intend to promote a learning paradigm shift through the application of peer review in education. A framework for this application is outlined, together with an account of results from experiences and a discussion about the skills that this approach exercises, especially with regard to widely accepted curricula and codes of ethics and professional conduct. Further research and development efforts are conjectured.

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