This work investigates the design of approximate arithmetic operator units used in the VLSI modular reduction (AxMOD) architecture. The AxMOD architecture herein proposed explores the following arithmetic operators: i...
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ISBN:
(数字)9798350391695
ISBN:
(纸本)9798350391701
This work investigates the design of approximate arithmetic operator units used in the VLSI modular reduction (AxMOD) architecture. The AxMOD architecture herein proposed explores the following arithmetic operators: i) two approximate iterative-based fixed-point and Goldschmidt (GLD) dividers, ii) five approximate adders (AxA): COPY adder, error-tolerant adder (ETA), lower-part OR adder (LOA), truncation (Trunc), and approximate parallel prefix adder (AxPPA), and iii) five approximate multipliers of approximate radix-4 multiplier units (AxRMU), dynamic range unbiased multiplier (DRUM), rounding-based approximate (RoBA), truncated multiplier (Trunc), and the leading one-bit based approximate (LoBA). Our demonstration of AxMOD’s efficiency using approximate arithmetic operators from the Pareto-optimal front illustrates the area and power-quality trade-off. Our results reveal that in fixed-point arithmetic, AxRMU with K = 16 and Trunc adder with K = 8 deliver energy savings of up to 4.14× compared to the state-of-the-art.
Approximate computing (AxC) offers opportunities to enhance computing efficiency by exploiting inherent error resilience. This study examines the security implications of AxC, focusing on adders, where Hardware Trojan...
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ISBN:
(数字)9798350391695
ISBN:
(纸本)9798350391701
Approximate computing (AxC) offers opportunities to enhance computing efficiency by exploiting inherent error resilience. This study examines the security implications of AxC, focusing on adders, where Hardware Trojan Horses (HTH) present significant risks. We propose a framework to inject HTH into approximate adders (AxAs), specifically the Approximate Parallel Prefix Adder (AxPPA), and assess their impact. The framework, implemented in MATLAB (code available at ***/MorganaMacedo/AxPPA_HTH), evaluates HTH injection into AxAs, analyzing error metrics (SSIM, NCC, MSE, MAE, and error-probability) and conducting logic-synthesis (LS) analysis to detect physical anomalies indicative of HTH presence. Our results demonstrate AxPPA’s resilience against HTH injection, with detection thresholds varying with approximation bit size. LS analysis shows AxPPA effectively detects HTHs across all bit approximations, outperforming LOA, particularly at K=16. AxPPA also achieves superior energy savings of 31.95% compared to LOA and notable area savings, highlighting its efficacy in HTH detection and performance optimization.
This work introduces a combined version of approximate adders (AxAs), joining approximate parallel prefix adders (AxPPA) with other AxAs from the literature (COPY, Truncation - TRUNC, and lower-part OR adder - LOA). W...
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ISBN:
(数字)9798350377200
ISBN:
(纸本)9798350377217
This work introduces a combined version of approximate adders (AxAs), joining approximate parallel prefix adders (AxPPA) with other AxAs from the literature (COPY, Truncation - TRUNC, and lower-part OR adder - LOA). We call this approach M-AxPPA (modified approximate parallel prefix adder) and investigate three specific versions: M-AxPPA-COPY, M-AxPPA-TRUNC, and M-AxPPA-LOA. We evaluate 315 different configurations, comparing our novel M-AxPPA to other AxAs proposed in the literature. We present pseudocode examples and investigate the accuracy quality, incorporating metrics like SSIM, NCC, MAE, MRE, and MRED. Additionally, we perform a trade-off analysis between accuracy quality and logic synthesis outcomes, underscoring the advantages of our M-AxPPA, notably the outstanding accuracy achieved by M-AxPPA-LOA (approaching 100%), with a substantial energy-saving.
The Affine Motion Estimation (AME) of the Versatile Video Coding (VVC) standard is a high-complexity task. The AME requires Affine Motion Compensation (MC) to be performed for $4\times 4$ subblocks, where the Motion...
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The Affine Motion Estimation (AME) of the Versatile Video Coding (VVC) standard is a high-complexity task. The AME requires Affine Motion Compensation (MC) to be performed for $4\times 4$ subblocks, where the Motion Vector relative to the $4\times 4$ subblock is adopted to define which of the 15 6-tap interpolation filters should be used to interpolate each sample of the $4\times 4$ subblock. This work presents a dedicated hardware implementation for the Affine MC of the VVC standard, where the ASIC synthesis results for this architecture for TSMC 40nm standard cells show an area requirement of 97.5k gates and power dissipation of 11.1mW when targeting the processing of 4K Ultra-High Definition (UHD) video at a frequency of 808MHz. To the best of the author's knowledge, this work presents the first hardware implementation of the VVC Affine MC in the literature.
The Versatile Video Coding (VVC) standard adopts the Affine Motion Estimation (AME) as one of its main novelties, which significantly contributed to the coding efficiency gains of VVC over previous standards. On the o...
The Versatile Video Coding (VVC) standard adopts the Affine Motion Estimation (AME) as one of its main novelties, which significantly contributed to the coding efficiency gains of VVC over previous standards. On the other hand, AME requires a very high computational effort for processing high-resolution videos in real-time, making dedicated hardware mandatory for battery-powered devices. Considering this scenario, this work presents a dedicated hardware design for the Affine Reconstructor of the VVC standard targeting an ASIC TSMC 40nm standard-cell technology. The synthesis results show 94.4k Gates of area requirements, with 15.36 mW of power dissipation when targeting the processing of 60 fps of 4K Ultra-High Definition (UHD) videos. To the best of the author's knowledge, the presented design is the first in the literature targeting the Affine Reconstructor of the VVC standard.
This article discusses the application of the peer review process as a pedagogical instrument for the promotion of written expression, collaborative work, critical thinking, and professional responsibility among Infor...
This article discusses the application of the peer review process as a pedagogical instrument for the promotion of written expression, collaborative work, critical thinking, and professional responsibility among Informatics and Engineering majors. The approach is introduced with a motivation, followed by a discussion about common principles of current learning paradigms and the peer review process. This work is being conducted in Brazil, where we intend to promote a learning paradigm shift through the application of peer review in education. A framework for this application is outlined, together with an account of results from experiences and a discussion about the skills that this approach exercises, especially with regard to widely accepted curricula and codes of ethics and professional conduct. Further research and development efforts are conjectured.
In recent years, 3D point cloud content has gained attention thanks to applications such as virtual, augmented or mixed reality, real-time immersive communications, and autonomous driving systems. However, raw point c...
In recent years, 3D point cloud content has gained attention thanks to applications such as virtual, augmented or mixed reality, real-time immersive communications, and autonomous driving systems. However, raw point clouds comprise large amount of data, and compression is mandatory to allow efficient transmission and storage. The MPEG group proposed the standard called Geometry-based Point Cloud Compression (G-PCC) implemented in the Test Condition Category 1 and 3 (TMC13) software. TMC13 can significantly reduce the amount of data in static point clouds, but requires a high computational cost making real-time compression unfeasible, especially for devices with limited computational power and energy resources. This paper presents a computational cost and coding efficiency evaluation of the G-PCC coding tools. Two main contributions are presented: first, a coding efficiency analysis of different G-PCC tools; second, a complexity profiling of the G-PCC coding steps aimed at understanding the computational effort distribution. This work provides the first complexity assessment of G-PCC. The presented results can help in the proposal of complexity reduction approaches for the development of more efficient versions of G-PCC for real-time purposes.
Intelligent computing techniques have a paramount importance to the treatment of cybersecurity incidents. In such Artificial Intelligence (AI) context, while most of the algorithms explored in the cybersecurity domain...
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The formation of consortia between public and private institutions to achieve projects with a common objective is a practice considered usual in Brazil. Due to the different destinations between these institutions, di...
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