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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Lourenço Mulling Morgana M. A. Rosa Rafael Soares Eduardo Costa Graduate Program on Computing Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9798350391695

ISBN: (纸本)9798350391701

This work investigates the design of approximate arithmetic operator units used in the VLSI modular reduction (AxMOD) architecture. The AxMOD architecture herein proposed explores the following arithmetic operators: i) two approximate iterative-based fixed-point and Goldschmidt (GLD) dividers, ii) five approximate adders (AxA): COPY adder, error-tolerant adder (ETA), lower-part OR adder (LOA), truncation (Trunc), and approximate parallel prefix adder (AxPPA), and iii) five approximate multipliers of approximate radix-4 multiplier units (AxRMU), dynamic range unbiased multiplier (DRUM), rounding-based approximate (RoBA), truncated multiplier (Trunc), and the leading one-bit based approximate (LoBA). Our demonstration of AxMOD’s efficiency using approximate arithmetic operators from the Pareto-optimal front illustrates the area and power-quality trade-off. Our results reveal that in fixed-point arithmetic, AxRMU with K = 16 and Trunc adder with K = 8 deliver energy savings of up to 4.14× compared to the state-of-the-art.

关键词： Energy consumption Accuracy Energy conservation Power quality Very large scale integration Dynamic range Adders System analysis and design Fixed-point arithmetic

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Evaluating the Resilience of the Approximate Parallel Prefix Adder (AxPPA) Against Hardware Trojan Horse Injection

Evaluating the Resilience of the Approximate Parallel Prefix...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Eloisa Barros Morgana M. A. Rosa Rodrigo Lopes Leonardo Antonietti Eduardo Costa Rafael Soares Graduate Program on Computing Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9798350391695

ISBN: (纸本)9798350391701

Approximate computing (AxC) offers opportunities to enhance computing efficiency by exploiting inherent error resilience. This study examines the security implications of AxC, focusing on adders, where Hardware Trojan Horses (HTH) present significant risks. We propose a framework to inject HTH into approximate adders (AxAs), specifically the Approximate Parallel Prefix Adder (AxPPA), and assess their impact. The framework, implemented in MATLAB (code available at ***/MorganaMacedo/AxPPA_HTH), evaluates HTH injection into AxAs, analyzing error metrics (SSIM, NCC, MSE, MAE, and error-probability) and conducting logic-synthesis (LS) analysis to detect physical anomalies indicative of HTH presence. Our results demonstrate AxPPA’s resilience against HTH injection, with detection thresholds varying with approximation bit size. LS analysis shows AxPPA effectively detects HTHs across all bit approximations, outperforming LOA, particularly at K=16. AxPPA also achieves superior energy savings of 31.95% compared to LOA and notable area savings, highlighting its efficacy in HTH detection and performance optimization.

关键词： Measurement Hardware Trojan horses Security MATLAB Adders System analysis and design Optimization Resilience Testing

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M-AxPPA: An Accurate and Energy-Efficient Modified Approximate Parallel Prefix Adder

M-AxPPA: An Accurate and Energy-Efficient Modified Approxima...

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Rodrigo Lopes Morgana da Rosa Eduardo da Costa Rafael Soares Graduate Program on Computing - Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9798350377200

ISBN: (纸本)9798350377217

This work introduces a combined version of approximate adders (AxAs), joining approximate parallel prefix adders (AxPPA) with other AxAs from the literature (COPY, Truncation - TRUNC, and lower-part OR adder - LOA). We call this approach M-AxPPA (modified approximate parallel prefix adder) and investigate three specific versions: M-AxPPA-COPY, M-AxPPA-TRUNC, and M-AxPPA-LOA. We evaluate 315 different configurations, comparing our novel M-AxPPA to other AxAs proposed in the literature. We present pseudocode examples and investigate the accuracy quality, incorporating metrics like SSIM, NCC, MAE, MRE, and MRED. Additionally, we perform a trade-off analysis between accuracy quality and logic synthesis outcomes, underscoring the advantages of our M-AxPPA, notably the outstanding accuracy achieved by M-AxPPA-LOA (approaching 100%), with a substantial energy-saving.

关键词： Measurement Accuracy Energy efficiency Logic Adders Electronic circuits

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Hardware Design for the Affine Motion Compensation of the VVC Standard

Hardware Design for the Affine Motion Compensation of the VV...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Marcello M. Muñoz Denis Maass Murilo Perleberg Luciano Agostini Marcelo Porto Graduate Program in Computing Federal University of Pelotas Pelotas Brazil

The Affine Motion Estimation (AME) of the Versatile Video Coding (VVC) standard is a high-complexity task. The AME requires Affine Motion Compensation (MC) to be performed for $4\times 4$ subblocks, where the Motion Vector relative to the $4\times 4$ subblock is adopted to define which of the 15 6-tap interpolation filters should be used to interpolate each sample of the $4\times 4$ subblock. This work presents a dedicated hardware implementation for the Affine MC of the VVC standard, where the ASIC synthesis results for this architecture for TSMC 40nm standard cells show an area requirement of 97.5k gates and power dissipation of 11.1mW when targeting the processing of 4K Ultra-High Definition (UHD) video at a frequency of 808MHz. To the best of the author's knowledge, this work presents the first hardware implementation of the VVC Affine MC in the literature.

关键词： Video coding VHDL Motion estimation Logic gates Parallel processing Hardware Motion compensation

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4K UHD@60fps Design For The VVC Affine Motion Estimation Reconstructor

4K UHD@60fps Design For The VVC Affine Motion Estimation Rec...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Marcello M. Muñoz Denis Maass Murilo Perleberg Luciano Agostini Guilherme Correa Marcelo Porto Graduate Program in Computing Federal University of Pelotas Pelotas Brazil

The Versatile Video Coding (VVC) standard adopts the Affine Motion Estimation (AME) as one of its main novelties, which significantly contributed to the coding efficiency gains of VVC over previous standards. On the other hand, AME requires a very high computational effort for processing high-resolution videos in real-time, making dedicated hardware mandatory for battery-powered devices. Considering this scenario, this work presents a dedicated hardware design for the Affine Reconstructor of the VVC standard targeting an ASIC TSMC 40nm standard-cell technology. The synthesis results show 94.4k Gates of area requirements, with 15.36 mW of power dissipation when targeting the processing of 60 fps of 4K Ultra-High Definition (UHD) videos. To the best of the author's knowledge, the presented design is the first in the literature targeting the Affine Reconstructor of the VVC standard.

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Peer Review in Education: Promoting Collaboration, Written Expression, Critical Thinking, and Professional Responsibility

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Education and Information Technologies 2003年第1期8卷 37-46页

作者： Kern, Vinícius Medina Saraiva, Luciana Martins dos Santos Pacheco, Roberto Carlos Computing Science and Engineering and UFSC Graduate Program in Production Engineering UNIVALI at São José Brazil Psychology and UFSC Graduate Program in Production Engineering UNIVALI at Biguaçu Brrazil UFSC Graduate Program in Production Engineering Brazil

This article discusses the application of the peer review process as a pedagogical instrument for the promotion of written expression, collaborative work, critical thinking, and professional responsibility among Informatics and Engineering majors. The approach is introduced with a motivation, followed by a discussion about common principles of current learning paradigms and the peer review process. This work is being conducted in Brazil, where we intend to promote a learning paradigm shift through the application of peer review in education. A framework for this application is outlined, together with an account of results from experiences and a discussion about the skills that this approach exercises, especially with regard to widely accepted curricula and codes of ethics and professional conduct. Further research and development efforts are conjectured.

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Coding Efficiency and Complexity Analysis of the Geometry-based Point Cloud Encoder

Coding Efficiency and Complexity Analysis of the Geometry-ba...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Cristiano Santos Leandro Tavares Eduardo Costa Gustavo Rehbein Guilherme Corrêa Marcelo Porto Graduate Program in Computing Federal University of Pelotas Pelotas Brazil

In recent years, 3D point cloud content has gained attention thanks to applications such as virtual, augmented or mixed reality, real-time immersive communications, and autonomous driving systems. However, raw point clouds comprise large amount of data, and compression is mandatory to allow efficient transmission and storage. The MPEG group proposed the standard called Geometry-based Point Cloud Compression (G-PCC) implemented in the Test Condition Category 1 and 3 (TMC13) software. TMC13 can significantly reduce the amount of data in static point clouds, but requires a high computational cost making real-time compression unfeasible, especially for devices with limited computational power and energy resources. This paper presents a computational cost and coding efficiency evaluation of the G-PCC coding tools. Two main contributions are presented: first, a coding efficiency analysis of different G-PCC tools; second, a complexity profiling of the G-PCC coding steps aimed at understanding the computational effort distribution. This work provides the first complexity assessment of G-PCC. The presented results can help in the proposal of complexity reduction approaches for the development of more efficient versions of G-PCC for real-time purposes.

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Evaluation of Distance Education through Blended Learning: Comparisons and Important Factors for the Learning Process

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Creative Education 2014年第2期5卷 70-74页

作者： Júlio C. G. Bertolin Ana Carolina Bertoletti De Marchi Graduate Program in Applied Computing University of Passo Fundo Passo Fundo Brazil Graduate Program in Education University of Passo Fundo Passo Fundo Brazil

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Case-based cybersecurity incident resolution 31

Case-based cybersecurity incident resolution

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31st International Conference on Software Engineering and Knowledge Engineering, SEKE 2019

作者： Colome, Marcelo Nunes, Raul Ceretta De Lima Silva, Luis Alvaro Graduate Program in Computer Science - PPGCC Applied Computing Department Federal University of Santa Maria Av. Roraima Campus UFSM Camobi Santa Maria RS Brazil

ISBN: (纸本)1891706489

Intelligent computing techniques have a paramount importance to the treatment of cybersecurity incidents. In such Artificial Intelligence (AI) context, while most of the algorithms explored in the cybersecurity domain aim to present solutions to intrusion detection problems, these algorithms seldom approach the correction procedures that are explored in the resolution of cybersecurity incident problems that already took place. In practice, knowledge regarding cybersecurity resolution data and procedures is being under-used in the development of intelligent cybersecurity systems, sometimes even lost and not used at all. In this context, this work proposes to integrate Case-Based Reasoning techniques and IODEF standard in order to retain concrete problem-solving experiences of cybersecurity incident resolution to be reused in the resolution of new incidents. Experimental results so far obtained with a Case-based Cybersecurity Incident Resolution System (CbCSecIRS) implemented show that information security knowledge can be retained in a reusable memory, so improving the resolution of new cybersecurity problems. © 2019 Knowledge Systems Institute graduate School. All rights reserved.

关键词： Intrusion detection

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Criteria Selection and Decision-Making Support in IT Governance: A Study via Fuzzy AHP Applied to a Multi-institutional Consortium

Criteria Selection and Decision-Making Support in IT Governa...

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International Conference on Information Technology and Systems, ICITS 2023

作者： de Oliveira, José Fábio de Sousa, Paulo Evelton Lemos Reis, Ana Carla Bittencourt Graduate Program in Applied Computing University of Brasília - UnB PPCA University Campus Darcy Ribeiro - Asa Norte DF CEP: 70910-900 Brasília Brazil

ISBN: (纸本)9783031332579

The formation of consortia between public and private institutions to achieve projects with a common objective is a practice considered usual in Brazil. Due to the different destinations between these institutions, divergences among decision-makers regarding the prioritization of actions may occur with some frequency. With this approach, this work seeks to minimize the impact of subjectivity in the prioritization of actions of a multi-institutional consortium, formed by public and private entities, with the support of Fuzzy logic and multi-criteria analysis to support the decision. Criteria and decision alternatives were identified and analyzed with the support of experts. At the end of the hierarchy, it was possible to present the top management of the Consortium with a proposal of ranked alternatives for optimizing the use of financial resources targeting IT Governance actions. © 2023, The Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Fuzzy logic

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