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AxRSU- : Higher-Order m-Bit Approximate Encoders for Radix- Squarer Units

Circuits, Systems, and Signal Processing 2024年第6期43卷 1-30页

作者： da Rosa, Morgana M. A. Paim, Guilherme da Costa, Eduardo A. C. Soares, Rafael Bampi, Sergio Graduate Program on Computing Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program in Microelectronics Federal University of RGS Porto Alegre Brazil Graduate Program in Electronics and Computer Engineering Catholic University of Pelotas Pelotas Brazil

Approximate computing has emerged as a design alternative to enhance design efficiency by capitalizing on the inherent error resilience observed in numerous applications. Various error-resilient and compute-intensive applications, such as signal, image and video processing, computer vision, and supervised machine learning, necessitate dedicated hardware accelerators for mean squared error estimation during runtime. In these application domains, using efficient arithmetic operators, particularly a squarer unit, represents one of the most effective strategies for low-power design. This work introduces an approximate Radix- $$2^{m}$$ squarer unit, denoted as AxRSU- $$2^{m}$$ . The proposed squarer unit employs m-bit approximate encoders to execute operations on m-bit data concurrently. The AxRSU- $$2^{m}$$ under consideration explores encoders with m equal to 2 (AxRSU-4), 3 (AxRSU-8), and 4 (AxRSU-16). These approximate encoders exhibit low complexity and diminish the necessary partial products operating on m bits simultaneously, thereby substantially enhancing energy efficiency and reducing circuit area in the AxRSU- $$2^{m}$$ . To illustrate the trade-off between error and quality in the AxRSU- $$2^{m}$$ , we apply it to an SSD (sum squared difference) hardware accelerator designed for video processing, with a square-accumulate serving as a case study. Our findings reveal a novel Pareto front, presenting eight optimal AxRSU- $$2^{m}$$ solutions that achieve accuracy levels ranging from 3.76 to 75.53%. These solutions yield energy savings ranging from 46.20 to 95.57% and circuit area reductions ranging from 37.68 to 66.73%.

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A Power-Efficient VLSI Multiplier Design Employing Radix-2m Squarer Unit and Adder Compressor

A Power-Efficient VLSI Multiplier Design Employing Radix-2m ...

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Leonardo Antonietti Morgana Da Rosa Rodrigo Lopes Eduardo Da Costa Rafael Soares Graduate Program on Computing - Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9798350377200

ISBN: (纸本)9798350377217

Multipliers are pivotal in numerous applications, including digital signal processing, image processing, and video processing. Nonetheless, their operation substantially increases power consumption for these applications. Therefore, applying strategies that can reduce power in this arithmetic operator is paramount. This paper presents a novel approach to optimize arithmetic units, focusing on multiplier units, through the integration of the Radix- $2^{m}$ squarer unit (RSU) and 4–2 adder/subtractor compressor (AC). Compared to the state-of-the-art, the proposed multiplier unit, termed MRSU (multiplier unit RSU-based), offers significant area-and energy-savings. The synthesis results show remarkable improvements in the MRSU Dadda 4–2 architecture, which achieves 14.35× more energy-savings for 8 bits, 4.87× for 16 bits, and 2.22× for 32 bits compared to the multiplier unit automatically selected by the logic-synthesis tool. Furthermore, compared to the Booth multiplier with the Dadda compression tree, MRSU Dadda 4–2 exhibits 1.67× more energy-savings for 8 bits, 1.93× for 16 bits, and 1.95× for 32 bits.

关键词： Image coding Power demand Focusing Digital signal processing Computer architecture Very large scale integration Energy efficiency Electronic circuits Adders Arithmetic

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Traffic Sign Classification based on Deep Learning

Traffic Sign Classification based on Deep Learning

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2023 IEEE International Conference on Automatic Control and Intelligent Systems, I2CACIS 2023

作者： Hongxing, Tian Caballero, Jonathan M. Hernandez, Alexander A. Technological University of the Philippines Graduate Program and External Studies Manila Philippines National University College of Computing and Information Technologies Manila Philippines

ISBN: (纸本)9798350321302

In the context of 5G communication, technologies such as the Internet of Things, big data, and supercomputers have been further developed, and artificial intelligence technology has also become one of the hot topics at present. In recent years, the image recognition technology of artificial intelligence has been pursued by most academic enthusiasts and has been rapidly developed. With the development of computer vision, a series of target detection algorithms have emerged in recent years. This paper classifies traffic signs based on the target detection algorithm of YOLOv5 and make use of the advantages of the accuracy and real-time performance of the YOLO algorithm. To restore the real traffic scene, different shooting angles and different shooting locations are prepared as data sets. Finally, to realize the detection and recognition of traffic signs and optimize the algorithm to improve the recognition rate. © 2023 IEEE.

关键词： Traffic signs

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Exploring Approximate Adders for an Energy-Efficient Pre-Processing Pan-Tompkins Algorithm VLSI Design

Exploring Approximate Adders for an Energy-Efficient Pre-Pro...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Léo Ribeiro Morgana M. A. Rosa Rafael Soares Eduardo Costa Graduate Program on Computing Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9798350391695

ISBN: (纸本)9798350391701

This work explores a set of approximate adders (COPY adder, error-tolerant adder - ETA, lower-part OR adder - LOA, truncation - Trunc, and approximate parallel prefix adder - AxPPA) to enhance a VLSI design for ECG signal preprocessing based on Pan-Tompkins algorithm (AxPTA) to improve energy efficiency and QRS complex detection. Validation with the MIT-BIH database confirms that the AxPTA design maintains excellent sensitivity and positive predictivity with reduced energy consumption and circuit area. The AxPTA with AxPPA achieves a 10.22% reduction in circuit size and saves 85.06% energy, with an acceptable 1.32% precision deviation. These results suggest that the AxPPA significantly boosts energy efficiency in the AxPTA design for ECG analysis, supporting the development of portable devices for continuous heart monitoring and cardiovascular disease prevention.

关键词： Energy consumption Sensitivity Databases Energy conservation Electrocardiography Very large scale integration Approximation algorithms Energy efficiency Adders System analysis and design

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AxMOD: VLSI Modular Reduction Design Exploring Approximate Arithmetic Units

AxMOD: VLSI Modular Reduction Design Exploring Approximate A...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Lourenço Mulling Morgana M. A. Rosa Rafael Soares Eduardo Costa Graduate Program on Computing Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9798350391695

ISBN: (纸本)9798350391701

This work investigates the design of approximate arithmetic operator units used in the VLSI modular reduction (AxMOD) architecture. The AxMOD architecture herein proposed explores the following arithmetic operators: i) two approximate iterative-based fixed-point and Goldschmidt (GLD) dividers, ii) five approximate adders (AxA): COPY adder, error-tolerant adder (ETA), lower-part OR adder (LOA), truncation (Trunc), and approximate parallel prefix adder (AxPPA), and iii) five approximate multipliers of approximate radix-4 multiplier units (AxRMU), dynamic range unbiased multiplier (DRUM), rounding-based approximate (RoBA), truncated multiplier (Trunc), and the leading one-bit based approximate (LoBA). Our demonstration of AxMOD’s efficiency using approximate arithmetic operators from the Pareto-optimal front illustrates the area and power-quality trade-off. Our results reveal that in fixed-point arithmetic, AxRMU with K = 16 and Trunc adder with K = 8 deliver energy savings of up to 4.14× compared to the state-of-the-art.

关键词： Energy consumption Accuracy Energy conservation Power quality Very large scale integration Dynamic range Adders System analysis and design Fixed-point arithmetic

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Evaluating the Resilience of the Approximate Parallel Prefix Adder (AxPPA) Against Hardware Trojan Horse Injection

Evaluating the Resilience of the Approximate Parallel Prefix...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Eloisa Barros Morgana M. A. Rosa Rodrigo Lopes Leonardo Antonietti Eduardo Costa Rafael Soares Graduate Program on Computing Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9798350391695

ISBN: (纸本)9798350391701

Approximate computing (AxC) offers opportunities to enhance computing efficiency by exploiting inherent error resilience. This study examines the security implications of AxC, focusing on adders, where Hardware Trojan Horses (HTH) present significant risks. We propose a framework to inject HTH into approximate adders (AxAs), specifically the Approximate Parallel Prefix Adder (AxPPA), and assess their impact. The framework, implemented in MATLAB (code available at ***/MorganaMacedo/AxPPA_HTH), evaluates HTH injection into AxAs, analyzing error metrics (SSIM, NCC, MSE, MAE, and error-probability) and conducting logic-synthesis (LS) analysis to detect physical anomalies indicative of HTH presence. Our results demonstrate AxPPA’s resilience against HTH injection, with detection thresholds varying with approximation bit size. LS analysis shows AxPPA effectively detects HTHs across all bit approximations, outperforming LOA, particularly at K=16. AxPPA also achieves superior energy savings of 31.95% compared to LOA and notable area savings, highlighting its efficacy in HTH detection and performance optimization.

关键词： Measurement Hardware Trojan horses Security MATLAB Adders System analysis and design Optimization Resilience Testing

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M-AxPPA: An Accurate and Energy-Efficient Modified Approximate Parallel Prefix Adder

M-AxPPA: An Accurate and Energy-Efficient Modified Approxima...

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Rodrigo Lopes Morgana da Rosa Eduardo da Costa Rafael Soares Graduate Program on Computing - Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9798350377200

ISBN: (纸本)9798350377217

This work introduces a combined version of approximate adders (AxAs), joining approximate parallel prefix adders (AxPPA) with other AxAs from the literature (COPY, Truncation - TRUNC, and lower-part OR adder - LOA). We call this approach M-AxPPA (modified approximate parallel prefix adder) and investigate three specific versions: M-AxPPA-COPY, M-AxPPA-TRUNC, and M-AxPPA-LOA. We evaluate 315 different configurations, comparing our novel M-AxPPA to other AxAs proposed in the literature. We present pseudocode examples and investigate the accuracy quality, incorporating metrics like SSIM, NCC, MAE, MRE, and MRED. Additionally, we perform a trade-off analysis between accuracy quality and logic synthesis outcomes, underscoring the advantages of our M-AxPPA, notably the outstanding accuracy achieved by M-AxPPA-LOA (approaching 100%), with a substantial energy-saving.

关键词： Measurement Accuracy Energy efficiency Logic Adders Electronic circuits

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Coding Efficiency and Complexity Analysis of the Geometry-based Point Cloud Encoder

Coding Efficiency and Complexity Analysis of the Geometry-ba...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Cristiano Santos Leandro Tavares Eduardo Costa Gustavo Rehbein Guilherme Corrêa Marcelo Porto Graduate Program in Computing Federal University of Pelotas Pelotas Brazil

In recent years, 3D point cloud content has gained attention thanks to applications such as virtual, augmented or mixed reality, real-time immersive communications, and autonomous driving systems. However, raw point clouds comprise large amount of data, and compression is mandatory to allow efficient transmission and storage. The MPEG group proposed the standard called Geometry-based Point Cloud Compression (G-PCC) implemented in the Test Condition Category 1 and 3 (TMC13) software. TMC13 can significantly reduce the amount of data in static point clouds, but requires a high computational cost making real-time compression unfeasible, especially for devices with limited computational power and energy resources. This paper presents a computational cost and coding efficiency evaluation of the G-PCC coding tools. Two main contributions are presented: first, a coding efficiency analysis of different G-PCC tools; second, a complexity profiling of the G-PCC coding steps aimed at understanding the computational effort distribution. This work provides the first complexity assessment of G-PCC. The presented results can help in the proposal of complexity reduction approaches for the development of more efficient versions of G-PCC for real-time purposes.

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Evaluation of an agent-based reinforcement learning framework for model-based testing 7

Evaluation of an agent-based reinforcement learning framewor...

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7th International Congress on Ambient Intelligence, Software Engineering, and e-Health and Mobile Health, AmITIC 2024

作者： Ramírez-Méndez, Jose Quesada-López, Christian University of Costa Rica Graduate Program in Computing and Informatics San Pedro Costa Rica University of Costa Rica Department of Computer Science and Informatics San Pedro Costa Rica

ISBN: (纸本)9798350364538

This study evaluates an agent-based reinforcement learning framework for model-based testing (MBT). The framework's performance was assessed on three key metrics: effectiveness and efficiency in achieving model coverage objectives, the quantity and uniqueness of generated test cases, and code coverage. The results show improved metrics for the framework compared to traditional testers in model coverage evaluation and test case metrics. Specifically, the framework achieved higher effectiveness and efficiency, generating a higher average number of test cases with a substantial proportion of unique cases, indicating more diverse and thorough testing. Additionally, the framework, along with random and greedy testers, achieved over 70% coverage across branch, method, and line code metrics. The framework showed slightly higher values in method and line coverage compared to other testers. The evaluation highlights the use of agent-based reinforcement learning to support model-based testing in planning test case generation, exploring models using multiple strategies, and learning guided by testing metrics. Future work will focus on further refining the framework learning model, including error coverage evaluation, and testing its applicability across different software systems. © 2024 IEEE.

关键词： Adversarial machine learning

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A Comparative Study on Manipulator Development in Multi-robotic Systems 1

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20th International Conference on Cooperative Design, Visualization and Engineering, CDVE 2023

作者： Çavuş, Özlem Şencan, İnanç Balcı, Ozan Architectural Design Computing Graduate Program Istanbul Technical University Istanbul Turkey Design Department of Architecture Katholieke Universiteit Leuven Leuven Belgium

ISBN: (数字)9783031438158

ISBN: (纸本)9783031438141

Robotic assembly of modular blocks has a great interest in multi-robotic studies in many disciplines. The existing studies primarily focus on context-specific tasks, especially in the self-assembly of robots, from an engineering perspective. However, considering a modular composition's entire design and fabrication process regarding mereological relationships is significant for the module's reuse in different pattern formations by mobile multi-robots. This study defines mobile robot swarms’ adaptability to the assembly-disassembly-reassembly (ADR) process to any-time change of the 3D pattern being assembled. Hence, the robot's manipulator needs to be compatible with picking up, carrying, attaching, and detaching the modules in the ADR process. This study questions the effects of the ADR process on manipulator development in multi-robotic systems. It aims to customize and develop manipulator systems beyond the existing gripper for multi-robot systems. Accordingly, it introduces a new conceptual understanding of manipulators’ taxonomy as friction-based and active and passive magnetic field-based end-effectors for the ADR process. Active indicates the use of electromagnets, whereas passive refers to using metal parts in the manipulator’s body. A physical experiment is conducted based on the above-stated taxonomies whose manipulators are printed in the Creality Ender3 and mounted to a mobile robot with a differential drive. The process is observed to discuss the introduced magnetic end-effectors, the system’s adaptability needs, and the pros and cons compared to the conventional gripper. © 2023, The Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Multipurpose robots

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