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检索条件"机构=Graduate Program in Computing - PPGC Video Technology Research Group - ViTech"

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H.264-to-AV1 video Transcoding Acceleration Based on Lightweight Machine Learning

H.264-to-AV1 Video Transcoding Acceleration Based on Lightwe...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Alex Borges Marcelo Porto Bruno Zatt Guilherme Correa Video Technology Research Group (ViTech) Graduate Program in Computing (PPGC) Federal University of Pelotas (UFPel) Pelotas Brazil

video streaming platforms have been using the H.264/AVC standard for a long time, even though it was released almost 20 years ago and much more efficient codecs are currently available. The AOMedia video 1 (AV1) format is an alternative with significant coding efficiency gains in comparison to H.264/AVC, besides being a royalty-free format. However, migrating legacy content from older to newer formats is a costly task, which requires long processing times. This work presents a solution for accelerating the H.264-to-AV1 transcoder based on machine learning. Sixteen decision tree models trained with data gathered during the H.264/AVC decoding and the AV1 encoding processes are proposed and implemented in the libaom reference software, leading to a complexity reduction of 18.96% at the cost of coding efficiency losses of 2.85% on average. To the best of the authors' knowledge, this is the first H.264-to-AV1 transcoding acceleration solution published in the literature.

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Efficient Hardware Design for the VVC Affine Motion Compensation Exploiting Multiple Constant Multiplication

Efficient Hardware Design for the VVC Affine Motion Compensa...

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IEEE Computer Society Annual Symposium on VLSI

作者： Marcello M. Muñoz Denis Maass Murilo Perleberg Luciano Agostini Marcelo Porto Graduate Program in Computing - PPGC Video Technology Research Group - ViTech Federal University of Pelotas - UFPel Pelotas Brazil

The Affine Motion Estimation (AME) is a new and high-complexity task of the Versatile video Coding (VVC) standard. The AME requires the Affine Motion Compensation (MC) to be performed for 4$\times$ 4 subblocks, where one among 156-tap interpolation filters was adopted to interpolate each sample of the 4$\times$ 4 subblock according to the motion vector relative to this subblock. This work presents two dedicated hardware implementations for the Affine MC of the VVC standard, the first focusing on the reduction of power dissipation and the second on the area requirement. The ASIC synthesis results of these architectures for TSMC 40nm standard cells show an area requirement of 54. 43k gates and power dissipation of 12. 8mW for the power efficient variant, while for the hardware efficient, the area requirement is 21. 91k gates and power dissipation of 14.41mW.

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Using Decision Trees to Accelerate the H.266/VVC-to-AV1 video Transcoding

Using Decision Trees to Accelerate the H.266/VVC-to-AV1 Vide...

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Brazilian Symposium on Computer Graphics and Image Processing (SIBGRAPI)

作者： Caroline Camargo Alex Borges Bruno Zatt Marcelo Porto Guilherme Correa Video Technology Research Group - ViTech Graduate Program in Computing - PPGC Federal University of Pelotas - UFPel Pelotas Brazil

H.266/NVC is the current state-of-the-art video coding format, launched in 2020. Despite its high capability to compress video, including ultra-high definition content, royalty costs may prevent its wide adoption. The AOMedia video 1 (AV1) format is an alternative with competitive coding efficiency, besides being a royalty-free format. However, migrating legacy content from one format to another is a costly task, which requires long processing times. This work presents a solution for accelerating the H.266/NVC-to-AV1 trans coding based on machine learning. Twelve decision tree models trained with data gathered during the H.266NVC decoding and the AV1 encoding processes are proposed and implemented in the libaom reference software, leading to a complexity reduction of 12.60 % at the cost of coding efficiency losses of 1.81 % on average. To the best of the authors' knowledge, this is the first H.266NVC-to-AV1 trans coding acceleration solution published in the literature.

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Multi-Objective optimized Complexity Control for the AV1 video Encoder

Multi-Objective optimized Complexity Control for the AV1 Vid...

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Picture Coding Symposium, PCS

作者： Gustavo Rehbein Isis Bender Guilherme Corrêa Luciano Agostini Marcelo Porto Federal University of Pelotas (UFPel) – Graduate Program in Computing (PPGC) Video Technology Research Group (ViTech)

ISBN: (纸本)9781665492584

AOMedia video 1 (AV1) is an open-source video encoding format launched in 2018 by Alliance for Open Media. To achieve high coding efficiency, AV1 brings significant innovations in comparison to its predecessor, the VP9 format. However, this came at the cost of a higher encoding complexity due to the newly introduced tools and block partitioning structures. To allow for wide deployment of AV1 in different multimedia devices, adjusting its encoding process according to the available computational resources is strongly desirable. Thus, this work presents an adaptive complexity controller for the AV1 encoder based on multi-objective optimization. Experimental results show that the proposed controller reduces encoding complexity in a target range from 10% to 40%, with satisfactory precision varying between 0.04 and 4.10 percentage points, and a BD-Rate between 0.22% and 5.24%.

关键词： Technological innovation Costs Sensitivity analysis Operating systems video sequences Focusing Media

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Fast Intra Mode Decision Using Machine Learning for the Versatile video Coding Standard

Fast Intra Mode Decision Using Machine Learning for the Vers...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Adson Duarte Bruno Zatt Guilherme Correa Daniel Palomino Video Technology Research Group (ViTech) Graduate Program in Computer Science (PPGC) Federal University of Pelotas (UFPel) Pelotas Brazil

This paper presents a fast intra mode decision solution for the VVC standard using machine learning. The idea is to reorder the evaluation of modes performed by the Rate-Distortion Optimization (RDO) process according to the modes occurrence rate. Based on the new evaluation order, three Decision Tree models were trained to skip the modes less likely to be chosen. The results show that the proposed solution achieves time savings of up to 15.57% with coding efficiency degradation of only 0.41% on average. When compared with related works, the proposed solution shows competitive results.

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Energy-Efficient Hardware Architecture for VVC TZS Using Approximate Subtractors

Energy-Efficient Hardware Architecture for VVC TZS Using App...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Rafael Ferreira Luciano Agostini Cláudio M. Diniz Bruno Zatt Video Technology Research Group (ViTech) Graduate Program in Computing (PPGC) Federal University of Pelotas (UFPel) Pelotas RS Brazil Microelectronics Group (GME) Graduate Program in Microelectronics (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

This paper investigates the impact of approximate subtractors in the hardware architecture of the Sum of Absolute Differences (SAD) computation within the Test Zone Search (TZS) algorithm, commonly used in current video encoders like the Versatile video Coding (VVC). Four state-of-the-art imprecise subtractors $(AppS, AXSC1, AXSC2, AXSC3)$ were analyzed across various video resolutions to assess their influence on computational effort, energy consumption, and coding efficiency. The results show that subtractors like $AppS_video$ and $AXCS1_video$ provide significant reductions in energy consumption with minimal impact on video coding quality. These findings are especially relevant for low-power devices and embedded systems, where energy efficiency is critical. The use of imprecise subtractors offers a promising tradeoff between computational efficiency and energy savings, making them a viable solution for high-performance video encoders.

关键词： video coding Energy consumption Embedded systems Energy conservation Energy resolution Computer architecture Energy efficiency Hardware Computational efficiency Power dissipation

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Multiversion Low-Power Hardware Accelerator for the AV1 Interpolation Filters

Multiversion Low-Power Hardware Accelerator for the AV1 Inte...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Daiane Freitas Mateus Grellert Cláudio M. Diniz Guilherme Correa Video Technology Research Group (ViTech) Graduate Program in Computing (PPGC) Federal University of Pelotas (UFPel) Embedded Computing Lab (ECL) Federal University of Santa Catarina (UFSC) PGMICRO Institute of Informatics (INF) Federal University of Rio Grande do Sul (UFRGS)

One of the new tools included in the AV1 video codec is the adaptive filtering scheme used in the sample interpolation process. This scheme includes three different filter families called Regular, Sharp and Smooth, offering high flexibility for motion estimation (ME) and motion compensation (MC). However, the high number of interpolation filters also leads to greater complexity and energy consumption, since the generation of samples at sub-pixel position is a costly process. This paper proposes a low-power and high-throughput hardware accelerator focused on the AV1 interpolation filters called Multiversion Interpolation Processor (MVIP). The accelerator includes the three AV1 interpolation filter families, with versions that employ operand isolation for power reduction in unused filters. The accelerator also includes a precise MVIP assuming the MC scenario, besides two approximate versions to reduce the cost on the ME scenario. The proposed design is able to process 8K video at 50fps in MC and 2,656.14 Msamples/sec in ME, with a power dissipation of 41.30mW.

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Efficient hardware design for the AV1 CDEF filter targeting 4K UHD videos 52

Efficient hardware design for the AV1 CDEF filter targeting ...

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52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020

作者： Zummach, Eduardo Palau, Roberta Palomino, Jones Goebel Daniel Agostini, Luciano Porto, Marcelo Postgraduate Program in Computing PPGC Video Technology Research Group ViTech Federal University of Pelotas UFPEL Brazil

ISBN: (纸本)9781728133201

Developed by the AOMedia industry consortium, the AOM video 1 (AV1) is an open-source and royalty-free video encoder released in June 2018. The Constrained Directional Enhancement Filter (CDEF) is one of the three AV1 in-loop filters and it is the focus of this work. The CDEF has the goal to reduce ringing artifacts generated with the encoding process, acting as a directional deringing filter. This paper presents a hardware design for the AV1 CDEF targeting real-time processing of 4K Ultra High Definition (UHD) videos. The architecture was synthesized to ASIC using the 40nm TSMC library, requiring 185 kgates and with a power dissipation of 43 mW when running at 93 MHz, reaching the frame rate of 60 frames per second (fps). To the best of the author's knowledge, there is no other work in the literature with dedicated hardware design for the AV1 CDEF. © 2020 IEEE

关键词： video signal processing

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Low-Complexity HEVC Transrating Based on Prediction Unit Mode Inheritance

Low-Complexity HEVC Transrating Based on Prediction Unit Mod...

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European Signal Processing Conference (EUSIPCO)

作者： Matheus Lindino Thiago Bubolz Bruno Zatt Daniel Palomino Guilherme Correa Video Technology Research Group (ViTech) Graduate Program in Computing (PPGC) Federal University of Pelotas (UFPel) Pelotas Brazil

ISBN: (数字)9789082797053

ISBN: (纸本)9781728150017

video transcoding for bit rate adaptation has become mandatory for over-the-top applications that deliver multimedia content in heterogeneous environments under different network conditions and user capabilities. As transcoding requires sequentially decoding and re-encoding the video bitstream, the computational cost involved in the process is too high, especially when considering current state-of-the-art codecs, such as the High Efficiency video Coding (HEVC). This work presents a fast HEVC transcoder for bit rate adaptation based on Prediction Unit (PU) mode inheritance, which uses information gathered from the HEVC decoding process to accelerate PU mode decision in the re-encoding process. Experimental results show that the proposed method achieves an average transrating time reduction of 42% at the cost of a bitrate increase of 0.54%.

关键词： Statistical analysis Bit rate Transcoding Streaming media Decoding Complexity theory High efficiency video coding

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Learning-Based Fast VVC Affine Motion Estimation

Learning-Based Fast VVC Affine Motion Estimation

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Fernando Sagrilo Marta Loose Ramiro Viana Gustavo Sanchez Guilherme Corrêa Luciano Agostini Graduate Program in Electrical Engineering (PPGEE) UNIPAMPA Alegrete RS Brazil Federal Institute of Farroupilha (IFFar) Jaguari Brazil Graduate Program in Computing (PPGC) UFPel Pelotas RS Brazil Video Technology Research Group (ViTech) UFPel Pelotas RS Brazil Federal Institute of Sertão Pernambucano (IFSertaoPE) Salgueiro PE Brazil

This paper presents a fast Affine Motion Estimation (AME) of Versatile video Coding (VVC) Standard, based on Machine Learning and using Random Forest (RF) classification method. This encoding approach develops an RF model for each block size. The models were trained with information extracted during the VVC encoding process of the current, parent, and neighboring Coding Units (CU). Each model is applied to predict whether the Affine Motion Estimation (AME) will be skipped or not for that CU size. The proposed solution achieves a reduction of 20% on average in AME encoding time, with an insignificant impact of 0.07% on BD-BR.

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