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检索条件"机构=Graduate Program in Computing - PPGC Video Technology Research Group - ViTech"

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Efficient Hardware Design for the AV1 CDEF Filter Targeting 4K UHD videos

Efficient Hardware Design for the AV1 CDEF Filter Targeting ...

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Eduardo Zummach Roberta Palau Jones Goebel Daniel Palomino Luciano Agostini Marcelo Porto Postgraduate Program in Computing - PPGC Video Technology Research Group - ViTech Federal University of Pelotas - UFPEL Brazil

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

Developed by the AOMedia industry consortium, the AOM video 1 (AV1) is an open-source and royalty-free video encoder released in June 2018. The Constrained Directional Enhancement Filter (CDEF) is one of the three AV1 in-loop filters and it is the focus of this work. The CDEF has the goal to reduce ringing artifacts generated with the encoding process, acting as a directional deringing filter. This paper presents a hardware design for the AV1 CDEF targeting real-time processing of 4K Ultra High Definition (UHD) videos. The architecture was synthesized to ASIC using the 40nm TSMC library, requiring 185 kgates and with a power dissipation of 43 mW when running at 93 MHz, reaching the frame rate of 60 frames per second (fps). To the best of the author's knowledge, there is no other work in the literature with dedicated hardware design for the AV1 CDEF.

关键词： videos Hardware FCC Decoding Damping Industries Encoding

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ERP-Based CTU Splitting Early Termination for Intra Prediction of 360 videos

ERP-Based CTU Splitting Early Termination for Intra Predicti...

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IEEE Visual Communications and Image Processing (VCIP)

作者： Bernardo Beling Iago Storch Luciano Agostini Bruno Zatt Sergio Bampi Daniel Palomino Video Technology Research Group (ViTech) Graduate Program in Computing (PPGC) Federal University of Pelotas (UFPel) Brazil Graduate Program in Computing (PPGC) Federal University of Rio Grande do Sul (UFRGS) Brazil

ISBN: (数字)9781728180687

ISBN: (纸本)9781728180694

This work presents an Equirectangular projection (ERP) based Coding Tree Unit (CTU) splitting early termination algorithm for the High Efficiency video Coding (HEVC) intra prediction of 360-degree videos. The proposed algorithm adaptively employs early termination in the HEVC CTU splitting based on distortion properties of the ERP projection, that generate homogeneous regions at the top and bottom portion of a video frame. Experimental results show an average of 24% time saving with 0.11% coding efficiency loss, significantly reducing the encoding complexity with minor impacts in the encoding efficiency. Besides, solution presents the best results considering the relation between time saving and coding efficiency when compared with all related works.

关键词： videos Encoding Complexity theory Distortion Two dimensional displays Prediction algorithms Standards

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A Low-Complexity Algorithm and Its Low-Power and High-Throughput Architecture for 3D-HEVC DMM-1 Encoding Tool

A Low-Complexity Algorithm and Its Low-Power and High-Throug...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Vinicius Borges Murilo Perleberg Vladimir Afonso Marcelo Porto Luciano Agostini Video Technology Research Group (ViTech) Federal University of Pelotas (UFPEL) Pelotas RS Brazil Postgraduate Program in Computing (PPGC) Video Technology Research Group (ViTech) Federal University of Pelotas (UFPEL) Pelotas RS Brazil Sul-rio-grandense Federal Institute (IFSul) Pelotas RS Brazil

ISBN: (数字)9781728134277

ISBN: (纸本)9781728134284

This paper presents a low-power and high-performance hardware design for the Depth Modeling Mode 1 (DMM-1) of the 3D-High Efficiency video Coding (3D-HEVC). The designed architecture is based on a low-complexity algorithm developed to reduce the DMM-1 computational effort and to avoid the use of memory. The architecture was described in VHDL, and the ASIC synthesis was performed for the TSMC 40nm technology. The synthesis results showed a gate count of 1,283k gates and a power dissipation of 51.36 mW, when running at 82 MHz. The designed architecture is capable of processing 3D 1080p videos with up to 11 views at 30 frames per second. The reached results surpass the published works in terms of throughput and power dissipation.

关键词： Encoding Computer architecture Hardware Calculators Tools video coding Three-dimensional displays

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Spatially Adaptive Intra Mode Pre-Selection for ERP 360 video Coding

Spatially Adaptive Intra Mode Pre-Selection for ERP 360 Vide...

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IEEE International Conference on Acoustics, Speech and Signal Processing

作者： Iago Storch Bruno Zatt Luciano Agostini Guilherme Correa Luis A. da Silva Cruz Daniel Palomino Video Technology Research Group (ViTech) Graduate Program in Computer Science (PPGC) Federal University of Pelotas (UFPel) Brazil Instituto de Telecomunicações University of Coimbra Portugal

ISBN: (数字)9781509066315

ISBN: (纸本)9781509066322

In this work, we propose a spatially adaptive HEVC intra mode pre-selection for equirectangular (ERP) 360 video coding. The proposed technique exploits the spatial characteristics of 360 video in the ERP projection to reduce the complexity of intra prediction mode selection. The number of intra modes evaluated in Rate-Distortion Optimization is reduced based on a score technique that is adaptive to the frame region being encoded. Results show that the proposed technique achieves a complexity reduction of 16.5% with low coding efficiency penalties.

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ASIC Solution for the Directional Intra Prediction of the AV1 Encoder Targeting UHD 4K videos

ASIC Solution for the Directional Intra Prediction of the AV...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Marcel Corrěa Luiz Neto Daniel Palomino Guilherme Corrěa Luciano Agostini Video Technology Research Group (ViTech) Federal University of Pelotas (UFPel) Brazil Graduate Program in Computing (PPGC) Federal University of Pelotas (UFPel) Brazil Sul-rio-grandense Federal Institute of Education Science and Technology (IFSul) Brazil

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

AOMedia video 1 (AV1), developed by the Alliance for Open Media consortium and released in 2018, is an open-source and royalty-free video format. It was designed to deliver substantial compression gains over its predecessor VP9 whilst keeping hardware feasibility and a practical decoding complexity. When compared to state-of-the-art formats, AV1 has more complex encoder tools, including the intra prediction which is the focus of this work. This paper presents a highly parallelized ASIC solution for the directional intra prediction module. It supports all 56 directional modes defined in AV1 and is able to process all combinations of block partitions. When synthesized to the TSMC 40nm technology with a target frequency of 1,296MHz, the proposed design used an area of 455.8K gates and showed a power dissipation and energy consumption per predicted sample of 40.92mW and 0.055pJ/sample, respectively. The reached throughput supports the processing of 60 frames per second for UHD 4K videos (3840×2160 pixels). No other work was found in the literature with a hardware design supporting the AV1 intra prediction directional modes.

关键词： videos video coding Vegetation Hardware Decoding Standards Encoding

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An UHD 4K@60fps Deblocking Filter Hardware Targeting the AV1 Decoder

An UHD 4K@60fps Deblocking Filter Hardware Targeting the AV1...

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Eduardo Zummach Roberta Palau Jones Goebel Felipe Sampaio Guilherme Correa Luciano Agostini Marcelo Porto Video Technology Research Group (ViTech) Federal University of Pelotas (UFPel) - Pelotas Brazil Graduate Program in Computing (PPGC) Federal University of Pelotas (UFPel) - Pelotas Brazil Federal Institute of Rio Grande do Sul (IFRS) - Farroupilha Brazil

ISBN: (数字)9781728160443

ISBN: (纸本)9781728160450

This paper presents a hardware design for the Deblocking Filter (DBF) in the AOM video 1 (AV1) decoder. The DBF is the first filter of the AV1 encoding loop, being used to attenuate blocking artifacts and to improve the subjective video quality. The presented hardware design is capable to process up to 56 samples per clock cycle, aiming at processing Ultra-High Definition (UHD) videos with 4098×2160 pixels (4K) at 60 frames per second when running at 16.2 MHz. The architecture was synthesized to ASIC using the 40nm TSMC library, requiring 39.35K gates and with a power dissipation of 3.96 mW. At the best of the authors' knowledge, this is the first hardware design targeting the AV1 DBF presented in the literature.

关键词： Finite impulse response filters Hardware Computer architecture Streaming media Decoding Filter banks Encoding

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A NEW HARDWARE FRIENDLY 2D-DCT HEVC COMPLIANT ALGORITHM AND ITS HIGH THROUGHPUT AND LOW POWER HARDWARE DESIGN

A NEW HARDWARE FRIENDLY 2D-DCT HEVC COMPLIANT ALGORITHM AND ...

引用

IEEE International Conference on Electronics, Circuits and Systems

作者： Luciano Almeida Braatz Antonio Carlos Schneider Beck Bruno Zatt Luciano Volcan Agostini Daniel Munari Palomino Marcelo Schiavon Porto Graduate Program in Computer Science (PPGC) Video Technology Research Group (ViTech) Federal University of Pelotas (UFPel) Brazil Institute of Informatics (INF) Federal University of Rio Grande do Sul (UFRGS) Brazil

This paper presents a hardware-friendly algorithm to maximize the throughput of the Discrete Cosine Transform (DCT) of the High Efficiency video Coding (HEVC), together with its hardware design. The Fast DCT (FCT) algorithm is based on the Cooley-Tuckey algorithm for the Fast Fourier Transform (FFT) with pre- and post-processing required to maintain the compliance with the HEVC. The resulting algorithm allows high throughput while maintaining low power dissipation. The designed hardware was synthesized for a 45-nm Nangate technology and it reaches a throughput of 81.28GSamples per second when consuming 12.33mW. Such energy efficiency and throughput surpass all related works in the literature.

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Exploring Heterogeneous Task-Level Parallelism in a BMA video Coding Application using System-Level Simulation

Exploring Heterogeneous Task-Level Parallelism in a BMA Vide...

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Brazilian Symposium on computing System Engineering (SBESC)

作者： Carlos Michel Betemps Mateus Santos De Melo Amir M. Rahmani Antonio Miele Nikil Dutt Bruno Zatt Postgraduate Program in Computing (PPGC) Video Technology Research Group (ViTech) Pelotas RS Brazil University of California Irvine (UCI) CA USA Politecnico di Milano (Polimi) Milano Italy

ISBN: (纸本)9781728102412;9781728102405

High abstraction level models can be used within the system-level simulation to allow rapid evaluations of architectural aspects in early Design Space Exploration (DSE) and direct the development decisions. Further, early DSE is of paramount importance in the specification of future Embedded Systems (ES) and its evaluation for applications with high computing demands and energy restrictions. This paper presents the exploration of Heterogeneous Task-Level Parallelism (HTLP) in a Block-Matching Algorithm (BMA) video coding application. HTLP means the creation and execution of simultaneous threads of kernels defined for different types of Processing Elements (PE) - e.g., CPU and GPU - but all for an equal purpose. We employ a BMA implementation as a case study, and its characteristics are used to explore the HTLP - in particular, its kernels for data preparation, SAD (sum of absolute differences) criteria calculation, and SAD values grouping. For the exploration, a system-level simulation framework (SAVE-htlp) is augmented, being able to support the HTLP. In the performed experiments, SAVE-htlp simulates workload and architecture models and explores 22 settings varying the PE type employed during the tasks' execution and the number of concurrent threads for each kernel. Execution time, performance, energy, and power results show HTLP settings overcoming CPU-only ones as well as those with solely GPUs to process its tasks.

关键词： Task analysis Object oriented modeling Unified modeling language Parallel processing Computational modeling Kernel Hardware

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Learning-Based Complexity Reduction and Scaling for HEVC Encoders

Learning-Based Complexity Reduction and Scaling for HEVC Enc...

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International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： Mateus Grellert Sergio Bampi Guilherme Correa Bruno Zatt Luis A. da Silva Cruz Graduate Program in Computing Federal University of Rio Grande do SuI Brazil Video Technology Research Group (ViTech) Federal University of Pelotas Brazil Dept. of Elect. and Comp. Engineering University of Coimbra Portugal

ISBN: (纸本)9781538646595

This article proposes a fast Coding Unit (CU) partition decision for use in HEVC encoders based on Decision Tree classifiers. The trees are employed in a modified low-complexity encoder that implements a fast CU partition decision algorithm. Using the proposed method, an average complexity reduction of 47.8% is achieved with a Bjontegaard Delta bitrate (BD-BR) loss of 0.24% in the Random Access coding configuration, and a 42.8% complexity reduction with a 0.19% BD-BR loss in the Low Delay B configuration. A decision threshold analysis is also presented to assess the rate-distortion-complexity trade-off of the proposed method at different complexity points, varying the complexity reduction from 28% (with a 0.04% loss in BD-BR) up to 60% (with a 3.6% BD-BR loss) using the Random Access configuration. A comparison with related works shows that the proposed method outperforms competing solutions in terms of both rate-distortion efficiency and complexity reduction.

关键词： Complexity theory Encoding Feature extraction Decision trees Training Rate-distortion Copper

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