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Interfacial-Layer-Free Ge0.95Si0.05Nanosheet FeFETs

IEEE Transactions on Electron Devices 2024年第3期71卷 1758-1763页

作者： Hsieh, Wan-Hsuan Chen, Yu-Rui Liu, Yi-Chun Zhao, Zefu Lee, Jia-Yang Tu, Chien-Te Huang, Bo-Wei Wang, Jer-Fu Lee, M.H. Liu, C.W. Graduate Institute of Electronics Engineering National Taiwan University Taipei10617 Taiwan Institute and Undergraduate Program of Electro-Optical Engineering Graduate School of Advance Technology National Taiwan University Taipei10617 Taiwan National Taiwan University Graduate School of Advance Technology Taipei10617 Taiwan Graduate Institute of Electronics Engineering Graduate Institute of Photonics and Optoelectronics Graduate School of Advanced Technology National Taiwan University Department of Electrical Engineering Taipei10617 Taiwan

The substantial memory window (MW) of 1.8 V is achieved by utilizing stacked two nanosheet (NS) gate-all-around (GAA) Ge0.95 Si0.05 ferroelectric field-effect transistors (FeFETs), employing a low write voltage of 2 V. The channel phosphorus concentration 1E18 cm-3 is used to erase the absence of interfacial layer (IL) can reduce the operation voltage. An isotropic wet etching process is employed for channel release. The stacked two NSs offer the advantages of reducing cell-to-cell variation and doubling the read current. Additionally, the stability of data storage is demonstrated with the data retention of >1E4 s, linearly extrapolated to a span of 10 years, and exhibiting high endurance >1E11 cycles. The thermal budget is as low as 400 °C. © 1963-2012 IEEE.

关键词： III-V semiconductors

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Compact Model Build Upon Dynamic Weighting Artificial Neural Network Approach for Complementary Field Effect Transistors

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IEEE Transactions on Electron Devices 2024年第1期71卷 246-253页

作者： Butola, Rajat Li, Yiming Kola, Sekhar Reddy National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Electrical Engineering and Computer Science International Graduate Program Hsinchu300093 Taiwan Institute of Pioneer Semiconductor Innovation The Institute of Artificial Intelligence Innovation National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Electrical Engineering and Computer Science International Graduate Program The Institute of Communications Engineering the Institute of Biomedical Engineering Department of Electronics and Electrical Engineering Hsinchu300093 Taiwan

In this work, a dynamic weighting-artificial neural network (DW-ANN) methodology is presented for quick and automated compact model (CM) generation. It takes advantage of both TCAD simulations for high accuracy and SPICE simulations for cost-effectiveness. This methodology is developed for gate-all-around (GAA) silicon (Si) nanosheet (NS) complementary field effect transistor (CFET), a potential candidate for future CMOS technology due to its innate properties. The critical process variation (PV) sources that severely degrade the CFET performance are estimated using DW-ANN. It reduces the computation cost and predicts the effects of PV sources with less than 1% error. Furthermore, a compact DW-ANN-based Verilog-A model has been developed that captures the dc as well as transient behavior accurately for circuit-level analysis. CFET-based circuits such as inverter, 6T-static random access memory (SRAM), and ring oscillator (RO) are characterized and implemented using DW-ANN-based CM. The overall average error of the model is reported as less than 2%. Therefore, the proposed device and circuit modeling approach provides a feasible solution for the rapid compact modeling of new emerging devices with good convergence and high accuracy. © 1963-2012 IEEE.

关键词： Neural networks

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Correntropy-Based Data Selective Adaptive Filtering

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IEEE Transactions on Circuits and Systems I: Regular Papers 2024年第2期71卷 754-766页

作者： Chien, Ying-Ren Wu, Sheng-Teng Tsao, Hen-Wai Diniz, Paulo S.R. Adaptive and Autonomous Communication Laboratory Department of Electrical Engineering National Ilan University Yilan City260007 Taiwan College of Electrical Engineering and Computer Science Graduate Institute of Communication Engineering National Taiwan University Taipei10617 Taiwan Program of Electrical Engineering Department of Electronics and Computer Engineering COPPE/Poli Universidade Federal do Rio de Janeiro Rio de Janeiro68504 Brazil

Data selection can be used in conjunction with adaptive filtering algorithms to avoid unnecessary weight updating and thereby reduce computational overhead. This paper presents a novel correntropy-based data selection method as an alternative to conventional data selection mechanisms based on squared error values. We developed a variable correntropy sensing algorithm to maximize the instantaneous correntropy function for the Gaussian kernel function to mitigate the impact of impulse noise and other forms of noise that can be disregarded in data selection. The proposed data selection mechanism can be implemented with any adaptive filtering algorithm. In simulations, the proposed method (implemented with the least mean squared algorithm) outperformed comparable error-based data selection schemes in terms of hit rate and miss rate, and the resulting weight updating ratio was close to the expected weight updating ratio. © 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.

关键词： Adaptive filters

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Quantitative Analysis of Ankle Spasticity Through Electromyography Signal

Quantitative Analysis of Ankle Spasticity Through Electromyo...

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2024 Medical Technologies Congress, TIPTEKNO 2024

作者： Gurluk, Ayse Bilal, Hafiz Muhammad Hocaoglu, Elif Living Robotics Laboratory Graduate School of Health Sciences Physiotherapy and Rehabilitation Program Istanbul Medipol University Istanbul Turkey Living Robotics Laboratory Graduate School of Engineering and Natural Sciences Electrical-Electronics Engineering and Cyber-Systems Program Istanbul Medipol University Istanbul Turkey Living Robotics Laboratory Department of Electrical and Electronics Engineering Istanbul Medipol University Istanbul Turkey

ISBN: (纸本)9798331529819

This study presents a more accurate evaluation method for assessing ankle spasticity compared to conventional goniometric techniques by utilizing measurements obtained from Inertial Measurement Units (IMU) and surface electromyography (sEMG) devices. Integrating IMU and EMG sensors provides substantial benefits for accurately determining the range of motion (ROM) associated with spasticity during targeted movements. In this study, the proposed method provides precise measurement and an objective evaluation of onset time detection of antagonistic muscle co-contraction, and accordingly the ROM of the actuated joint. Moreover, the implementation of cost-effective wearable sensors enables the monitoring of muscle spasticity in clinical environments and can be particularly valuable in regions with limited access to experienced therapists, providing a more efficient approach to tracking spasticity levels. © 2024 IEEE.

关键词： Electromyography

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Measurement of renal blood flow in a rat model using diffuse correlation spectroscopy

Measurement of renal blood flow in a rat model using diffuse...

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Microscopy Histopathology and Analytics, Microscopy 2024 - Part of Optica Biophotonics Congress: Biomedical Optics

作者： Nakabayashi, Mikie Ono, Yumie Electrical Engineering Program Graduate School of Science and Technology Meiji University Kanagawa Japan Department of Electronics and Bioinformatics School of Science and Technology Meiji University Kanagawa Japan

ISBN: (纸本)9781957171340

关键词： Detectors Laser sources Lasers Near infrared Photon counting Spectroscopy

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Multiplexed Nanoscopy via Buffer Exchange

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ACS Nano 2024年第34期18卷 23445-23456页

作者： Chang, Ting-Jui Ben Yang, T. Tony Department of Electrical Engineering National Taiwan University Taipei10617 Taiwan Graduate Institute of Biomedical Electronics and Bioinformatics National Taiwan University Taipei10617 Taiwan Department of Physics National Taiwan University Taipei10617 Taiwan Nano Science and Technology Program Taiwan International Graduate Program Academia Sinica and National Taiwan University Taipei10617 Taiwan

Understanding cellular functions, particularly in their intricate complexity, can greatly benefit from the spatial mapping of diverse molecules through multitarget single-molecule localization microscopy (SMLM). Existing methodologies, primarily restricting the encoding dimensions to color and lifetime or requiring cyclic staining, often involve broad chromatic detection, specialized optical configurations, or sophisticated labeling techniques. Here, we propose a simple approach called buffer-exchange stochastic optical reconstruction microscopy (beSTORM), which introduces an additional dimension to differentiate between single molecules irrespective of their spectral properties. This method leverages the distinguishable photoblinking responses to distinct buffer conditions, offering a straightforward yet effective means of fluorophore discrimination. Through buffer exchanges, beSTORM achieves multitarget SMLM imaging with minimal crosstalk. Direct integration with expansion microscopy (ExM) demonstrates its capability to resolve up to six proteins at the molecular level within a single emission color without chromatic aberration. Overall, beSTORM presents a highly compatible imaging platform, promising significant advancements in highly multiplexed nanoscopy for exploring multiple targets in biological systems with nanoscale precision. © 2024 The Authors. Published by American Chemical Society.

关键词： Stochastic systems

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Overview of Versatile Video Coding (H.266/VVC) and Its Coding Performance Analysis

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IEIE Transactions on Smart Processing and Computing 2023年第2期12卷 122-154页

作者： Lee, Minhun Song, HyeonJu Park, Jeeyoon Jeon, Byeungwoo Kang, Jungwon Kim, Jae-Gon Lee, Yung-Lyul Kang, Je-Won Sim, Donggyu Department of Computer Engineering Kwangwoon University Seoul Korea Republic of Department of Computer Engineering Sejong University Seoul Korea Republic of Department of Electrical and Computer Engineering Sungkyunkwan University Kyunggi-do Korea Republic of Communication and Media Research Laboratory Electronics and Telecommunications Research Institute Deajeon Korea Republic of School of Electronics and Information Engineering Korea Aerospace University Kyunggi-do Korea Republic of Department of Electronic and Electrical Engineering Graduate Program in Smart Factory Ewha Womans University Seoul Korea Republic of

Versatile Video Coding (H.266/VVC) is the newest video coding standard jointly developed by the Joint Video Experts Team (JVET), which is organized by the ITU-T Video Coding Experts Group (VCEG) and the ISO/IEC Moving Picture Experts Group (MPEG). H.266/VVC provides about 40% bitrate reduction compared with High Efficiency Video Coding (H.265/HEVC) for the same visual quality. This paper introduces in detail the core structure of H.266/VVC by highlighting its features within block partitioning structure, intra/inter prediction, transform, quantization, and in-loop filtering, compared to its predecessor (H.265/HEVC). H.266/VVC yields significantly improved the coding performance, but it increased the computational complexity, particularly for the encoder side, which remains a problem to be tackled for successful commercialization in the future. This paper examined the statistical performance of H.266/VVC coding tools from the bitstreams encoded by the VVC test model (VTM12.0) encoder through rate-distortion optimization under the JVET common test conditions. In addition, the complexity and performance analyses are conducted on the block partitioning structure and group of picture structure. It is expected that an optimized H.266/VVC encoder can be designed and developed by minimizing the coding loss based on the analysis data. © 2023 Institute of electronics and Information Engineers. All rights reserved.

关键词： Image compression

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A Comprehensive Technique Based on Machine Learning for Device and Circuit Modeling of Gate-All-Around Nanosheet Transistors

IEEE Open Journal of Nanotechnology

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IEEE Open Journal of Nanotechnology 2023年 4卷 181-194页

作者： Butola, Rajat Li, Yiming Kola, Sekhar Reddy National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Electrical Engineering and Computer Science International Graduate Program Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Institute of Communications Engineering the Institute of Biomedical Engineering the Department of Electronics and Electrical Engineering the Institute of Pioneer Semiconductor Innovation and the Institute of Artificial Intelligence Innovation Hsinchu300093 Taiwan

Machine learning (ML) is poised to play an important part in advancing the predicting capability in semiconductor device compact modeling domain. One major advantage of ML-based compact modeling is its ability to capture complex relationships and patterns in large datasets. Therefore, in this paper a novel design scheme based on dynamically adaptive neural network (DANN) is proposed to develop fast and accurate compact model (CM). This framework constitutes a powerful yet computationally efficient methodology and exhibits emergent dynamic behaviors. This paper demonstrates that the compact model based on ML can be designed to replicate the performance of conventional compact model for nanodevices. For this work, gate-all-around (GAA) nanosheet (NS) device characteristics are comprehensively analyzed for process variability sources using the proposed model. The device geometry parameters such as channel length, nanosheet width and nanosheet thickness are fed as input features to the DANN model. The adaptive neural network learns dynamically by updating weights of the model in accordance with the input features and achieves accurate neural weight convergence. The proposed model predicted the electrical characteristics of NS devices with less than 1% error rate. The model is also implemented and validated for the simulations of digital circuit designs such as inverter, and logic gates. ©;2023 The Authors.

关键词： Circuit simulation

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Temperature-Dependent Hydrogen Modulations of Ultra-Scaled a-IGZO Thin Film Transistor Under Gate Bias Stress

IEEE Open Journal of Nanotechnology

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IEEE Open Journal of Nanotechnology 2024年 5卷 9-16页

作者： Aslam, Muhammad Chang, Shu-Wei Chuang, Min-Hui Chen, Yi-Ho Lee, Yao-Jen Li, Yiming Parallel and Scientific Computing Laboratory National Yang Ming Chiao Tung University Hsinchu300093 Taiwan Electrical Engineering and Computer Science International Graduate Program National Yang Ming Chiao Tung University Hsinchu300093 Taiwan Department of Electrical Engineering National Cheng Kung University Tainan701401 Taiwan Institute of Communications Engineering National Yang Ming Chiao Tung University Hsinchu300093 Taiwan Graduate Degree Program of College of Electrical and Computer Engineering National Yang Ming Chiao Tung University Hsinchu300093 Taiwan Institute of Pioneer Semiconductor Innovation National Yang Ming Chiao Tung University Hsinchu300093 Taiwan Institute of Biomedical Engineering National Yang Ming Chiao Tung University Hsinchu300093 Taiwan Department of Electronics and Electrical Engineering National Yang Ming Chiao Tung University Hsinchu300093 Taiwan

Recently, a-IGZO has advanced toward the next-generation electronics system because of its compatibility with complementary metal oxide semiconductor (CMOS) and back-end-of-line (BOEL) based systems. A systematic electrical characterization of a-IGZO TFT related to reliability issues, such as positive bias temperature stress (PBTS) and negative bias temperature stress (NBTS), would entitle its integration into novel electronics systems. Unexpectedly, PBTS is characterized by the transition of positive Vth shift to negative Vth shift (ΔVth, the positive shift followed by the stress and temperature activated negative shift). This transition is attributed to charge trapping/trap-site generations and hydrogen migration to the active layer. The ΔVth shift mechanism depends on the temperature and voltage stress. On the other hand, a negative ΔVth shift has been observed during the NBTS operation and could be attributed to the hole trapping at the interface of GI/IGZO. An effective suppression of the gate leakage current has also been observed during reliability tests. Simulation results reveal a pronounced potential at the edges of source and drain regions, and considered the origin of hydrogen migration into the IGZO layer. Thermal image results also reveal the strong temperature/potential distribution at the edges of the source/drain regions, indorsing the simulation results. © 2020 IEEE.

关键词： Oxide semiconductors

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Statistical Device Simulation and Machine Learning of Process Variation Effects of Vertically Stacked Gate-All-Around Si Nanosheet CFETs

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IEEE Transactions on Nanotechnology 2024年 23卷 386-392页

作者： Kola, Sekhar Reddy Li, Yiming Butola, Rajat National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Electrical Engineering and Computer Science International Graduate Program Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Department of Electronics and Electrical Engineering Institute of Communications Engineering Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Institute of Biomedical Engineering Institute of Pioneer Semiconductor Innovation Institute of Artificial Intelligence Innovation Hsinchu300093 Taiwan

In this study, we report the process variation effect (PVE) including the work function fluctuation (WKF) on the DC/AC characteristic fluctuation of stacked gate-all-around silicon complementary field-effect transistors (CFETs). The PVE affects characteristic fluctuation significantly;in particular, for the variability of off-state current. Owing to the bottom channel of a fin-type, the P-FET suffers from the worst off-state current fluctuation (more than 200% variation) compared to the N-FET. The device variability induced by the WKF is marginal because of amorphous-type metal grains. As input features to an artificial neural network (ANN) model, low and high work function values, as well as parameters of PVE that have prevalent effects on CEFT transfer characteristics are further considered and modeled. The estimated values of R2-score prove that the ANN model properly grasps information from the dataset successfully;thus, it can be used to model emerging CFETs for circuit simulation. © 2002-2012 IEEE.

关键词： Neural networks

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