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A Low-Power Level-2 Discrete Haar Wavelet Transform with Approximate Adders for ECG Signal 16

A Low-Power Level-2 Discrete Haar Wavelet Transform with App...

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16th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2025

作者： Seidel, Henrique Da Rosa, Morgana Lopes, Rodrigo Da Costa, Eduardo Soares, Rafael Graduate Program on Computing Pelotas Brazil Graduate Program on Electronic Engineering and Computing Pelotas Brazil

ISBN: (纸本)9798331522124

We present an energy-efficient implementation of the level-2 Pruned Discrete Haar Wavelet Transform (PDHWT-2) for R-peak detection in ECG signals. Approximate computing techniques were employed, including five well-established approximate adders (AxPPA, COPY, ETA-I, LOA, and Trunc) and bit truncation (T), to reduce energy consumption while maintaining accuracy above 99% for reliable R-peak detection. By focusing on the second-level detail coefficient (D2) for peak detection and pruning the approximation coefficient, the PDHWT-2 design achieves significant reductions in computational complexity. The architecture, evaluated with ECG signals from the MIT-BIH database, maintained accuracy above 99% even with aggressive bit truncation and approximation, ensuring reliable medical-grade analysis. Integration of approximate adders (AxAs) and truncation enabled significant power and area savings. Specifically, the use of the AxPPA demonstrated power savings of up to 40% with area reductions of around 45%, making the PDHWT-2 a highly efficient solution for low-power ECG monitoring systems. © 2025 IEEE.

关键词： Image reconstruction

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Exploring Approximate Adders for Accuracy- and Energy-Quality VLSI Watermarking Systems Design 16

Exploring Approximate Adders for Accuracy- and Energy-Qualit...

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16th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2025

作者： Da Rosa, Morgana Da Costa, Eduardo Soares, Rafael Graduate Program on Computing Pelotas Brazil Graduate Program on Electronic Engineering and Computing Pelotas Brazil

ISBN: (纸本)9798331522124

Approximate computing (AxC) has emerged as a viable alternative to enhance computational efficiency by leveraging the intrinsic error resilience of many applications. One of the leading strategies of AxC involves exploring different approximation adder (AxA) configurations as a viable form of reducing power consumption in many applications. This work explores the use of AxAs in a hybrid watermarking technique that combines discrete Haar-Wavelet (DHWT) and discrete cosine transforms (DCT). The proposed hybrid method, HyDHWCT, integrates these transforms to improve robustness and imperceptibility in watermarking systems while optimizing for energy efficiency. We evaluate the performance of various AxAs, including Copy, ETA, LOA, Truncation (Trunc), VLSPPAs, and the AxPPA, regarding energy consumption, circuit area, and error resilience. Our results demonstrate that the AxPPA-based HyDHWCT offers superior accuracy and energy-quality trade-offs over other state-of-the-art AxAs. Specifically, the AxPPA on HyDHWCT with K = 1 achieves up to 72.85% energy savings and 88.32% area savings compared to the exact HyDHWCT while maintaining high accuracy, with a normalized cross-correlation (NC) of 0.9949 and a structural similarity (SSIM) of 0.9920 for the extracted watermark. These results make the AxPPA-based HyDHWCT a highly effective solution for robust and energy-efficient watermarking systems. © 2025 IEEE.

关键词： Energy efficiency

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An Ultra Low-Energy VLSI Approximate Discrete Haar Wavelet Transform for ECG Data Compression 30

An Ultra Low-Energy VLSI Approximate Discrete Haar Wavelet T...

引用

30th IEEE International Conference on electronics, Circuits and Systems, ICECS 2023

作者： Cardozo, Arthur Rosa, Morgana M. A. Soares, Rafael Costa, Eduardo Bampi, Sergio Graduate Program on Computing Pelotas Brazil Graduate Program on Electronic Engineering and Computing Pelotas Brazil Porto Alegre Brazil

ISBN: (纸本)9798350326499

This work proposes an ultra-low-energy ECG data compression with VLSI DHWT-based (discrete Haar wavelet transform) architecture to enable storage and transmission in resource-constrained environments. We present original, pruned, and approximate DHWT (ODHWT, PDHWT, and AxDHWT, respectively) hardware architectures for ECG data compression at ultra-high energy efficiency. Our best proposal employing the AxDHWT hardware architecture requires just five additions only. Using a PDHWT technique to improve energy efficiency observes the evolution of the signal-to-noise ratio and the ultimate impact on the ECG data compression application. The DHWT-based configurations architecture proposal achieves a minimum compression ratio of 0.125 (i.e., 1/8) and a PRD (percent root difference) © 2023 IEEE.

关键词： Digital storage

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New Energy-Efficient 3-2 and 4-2 Approximate Adder Compressors Topologies 30

New Energy-Efficient 3-2 and 4-2 Approximate Adder Compresso...

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30th IEEE International Conference on electronics, Circuits and Systems, ICECS 2023

作者： Lopes, Rodrigo Antonietti, Leonardo Rosa, Morgana M. A. Costa, Eduardo Soares, Rafael Bampi, Sergio Graduate Program on Computing Pelotas Brazil Graduate Program on Electronic Engineering and Computing Pelotas Brazil PPGC & PGMICRO - Informatics Institute Porto Alegre Brazil

ISBN: (纸本)9798350326499

Addition units are present across many computational kernels inherent in various error-tolerant applications, including machine learning, signal, image, and video processing. Notably, adder compressors are the target when high speed and low power are the main design concerns. This work introduces energy-efficient structures of 3-2 approximate adder compressors (Ax3-2) and three distinct versions of 4-2 approximate adder compressors (Ax4-2). We compared our proposed Ax3-2 and Ax4-2 compressors with state-of-the-art energy-efficient approximate adder compressors (AxACs). Both Ax3-2 and Ax4-2 models passed through rigorous tests as standalone units. Furthermore, we integrated the Ax4-2 models into an essential application kernel appearing in video coding, i.e., the Sum Squared Differences (SSD) video accelerator. We introduce Ax3-2 and Ax4-2 that yield a new Pareto front concerning both energy-quality and area-quality trade-offs, thereby demonstrating a marked improvement over the prevailing state-of-the-art energy-efficient AxACs. © 2023 IEEE.

关键词： Adders

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Accuracy-, Delay- and Area-Driven Evaluation of Lower-Part Approximate Parallel Prefix Adder 30

Accuracy-, Delay- and Area-Driven Evaluation of Lower-Part A...

引用

30th IEEE International Conference on electronics, Circuits and Systems, ICECS 2023

作者： Rosa, Morgana M. A. Costa, Eduardo Soares, Rafael Bampi, Sergio Pelotas Brazil Graduate Program on Electronic Engineering and Computing Pelotas Brazil Porto Alegre Brazil

ISBN: (纸本)9798350326499

This work proposes an accuracy-driven evaluation model of an approximate adder (AxA) called an approximate parallel prefix adder (AxPPA). It explores the significance of approximate computing (AxC) in optimizing performance and energy efficiency in computer systems by accepting minor accuracy trade-offs. We examine the AxPPA through a meticulous error analysis model and an automated analysis framework that comprehensively evaluates area and delay based on the fundamental equations of parallel prefix adders (PPAs). Additionally, it emphasizes the importance of lower-part approximation in adders, effectively addressing the elongation of carry chains and enhancing overall efficiency. The choice of approximation method directly impacts computational accuracy, resulting in variations in the number of approximated bits and carry chain length for a given tolerance level. Conducting a thorough comparison of accuracy trade-offs requires a unique design and simulation for each unit and approximation level, which can be time-consuming, particularly in larger circuits. Therefore, the proposed approach facilitates the exploration of larger circuit design space encompassing multiple AxAs, significantly minimizing time investment. In our experiments, the accuracy-driven evaluation of the lower part approximation method in AxA took 71.268 milliseconds for 1 million random inputs, with a K -bits approximation ranging from 1 to 16. The results indicate that AxPPA exhibits a minor error magnitude among the explored literature AxAs, being approximately 50.97% more accurate on average. © 2023 IEEE.

关键词： Adders

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An Optimized VLSI Exponential Unit Design Exploring Efficient Arithmetic Operation Strategies 30

An Optimized VLSI Exponential Unit Design Exploring Efficien...

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30th IEEE International Conference on electronics, Circuits and Systems, ICECS 2023

作者： Da Costa, Patrícia Da Rosa, Morgana Soares, Rafael Da Costa, Eduardo Bampi, Sergio Federal University of Rio Grande Do Sul Graduate Program on Microelectronics Porto Alegre Brazil Graduate Program on Computing Pelotas Brazil Graduate Program on Electronic Engineering and Computing Pelotas Brazil Porto Alegre Brazil

ISBN: (纸本)9798350326499

This work presents an optimized exponential function VLSI hardware design by Taylor series expansion. The proposed architecture implements the exponential by approximating the logic design of a 4th-order Taylor series and explores efficient CMOS arithmetic operation strategies. It implements a shift-based divider and explores an efficient 4-2 adder compressor in the adder tree. The proposal with a -7 to 11 input values range shows an output error of around 2% of MRED with a reduced energy consumption of 3.63 pJ/operation for 32-bit output. For a 64-bit output, the energy per operation of the VLSI exponential unit is 14.97pJ/op, being able to process a more comprehensive input range (i.e., -14 to 22) for a negligible mean output error of around 1.7% of MRED. © 2023 IEEE.

关键词： Adders

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A Low-Power Level-2 Discrete Haar Wavelet Transform with Approximate Adders for ECG Signal

A Low-Power Level-2 Discrete Haar Wavelet Transform with App...

引用

IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Henrique Seidel Morgana da Rosa Rodrigo Lopes Eduardo da Costa Rafael Soares Graduate Program on Computing Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

We present an energy-efficient implementation of the level-2 Pruned Discrete Haar Wavelet Transform (PDHWT-2) for R-peak detection in ECG signals. Approximate computing techniques were employed, including five well-established approximate adders (AxPPA, COPY, ETA-I, LOA, and Trunc) and bit truncation (T), to reduce energy consumption while maintaining accuracy above 99% for reliable R-peak detection. By focusing on the second-level detail coefficient $(D_{2})$ for peak detection and pruning the approximation coefficient, the PDHWT-2 design achieves significant reductions in computational complexity. The architecture, evaluated with ECG signals from the MIT-BIH database, maintained accuracy above 99% even with aggressive bit truncation and approximation, ensuring reliable medical-grade analysis. Integration of approximate adders (AxAs) and truncation enabled significant power and area savings. Specifically, the use of the AxPPA demonstrated power savings of up to 40% with area reductions of around 45%, making the PDHWT-2 a highly efficient solution for low-power ECG monitoring systems.

关键词： Accuracy Approximate computing Transforms Computer architecture Electrocardiography Energy efficiency Discrete wavelet transforms Reliability Adders Monitoring

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Exploring Approximate Adders for Accuracy- and Energy-Quality VLSI Watermarking Systems Design

Exploring Approximate Adders for Accuracy- and Energy-Qualit...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Morgana da Rosa Eduardo da Costa Rafael Soares Graduate Program on Computing Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

关键词： Energy consumption Accuracy Energy conservation Watermarking DH-HEMTs Energy efficiency Robustness Discrete cosine transforms Adders Resilience

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Exploring Approximate Adders for Energy-Efficient Discrete Walsh-Hadamard Transform

Exploring Approximate Adders for Energy-Efficient Discrete W...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Leonardo Antonietti Rodrigo Lopes Morgana da Rosa Eloisa Barros Eduardo da Costa Rafael Soares Graduate Program on Computing - Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

This work investigates the use of the Discrete Walsh-Hadamard Transform (DWHT) for cryptographic applications, particularly within resource-constrained environments like microcontrollers such as RISC-V. DWHT's use of adder and subtractor arithmetic operations makes it highly suitable for low-complexity algorithms. In order to enhance efficiency further, our work integrates various approximate adders (AxAs) such as AxPPA, COPY, ETA-I, LOA, and Trunc into both forward (DWHT) and inverse (IDWHT) transform architectures. Our approach outperforms existing methods from the literature regarding accuracy metrics, particularly for lower approximation levels $(K=1\ \text{to}\ K=3)$ , with substantial improvements in PSNR and SSIM. Additionally, our designs significantly reduce power and area compared to existing hardware implementations, show-casing their potential for deployment in real-world cryptographic and hardware security applications.

关键词： Measurement Accuracy Microcontrollers Circuits and systems Hardware security Transforms Energy efficiency Encryption Adders Arithmetic

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A Power-Efficient VLSI Multiplier Design Employing Radix-2m Squarer Unit and Adder Compressor

A Power-Efficient VLSI Multiplier Design Employing Radix-2m ...

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IEEE International Conference on electronics, Circuits and Systems (ICECS)

作者： Leonardo Antonietti Morgana Da Rosa Rodrigo Lopes Eduardo Da Costa Rafael Soares Graduate Program on Computing - Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9798350377200

ISBN: (纸本)9798350377217

Multipliers are pivotal in numerous applications, including digital signal processing, image processing, and video processing. Nonetheless, their operation substantially increases power consumption for these applications. Therefore, applying strategies that can reduce power in this arithmetic operator is paramount. This paper presents a novel approach to optimize arithmetic units, focusing on multiplier units, through the integration of the Radix- $2^{m}$ squarer unit (RSU) and 4–2 adder/subtractor compressor (AC). Compared to the state-of-the-art, the proposed multiplier unit, termed MRSU (multiplier unit RSU-based), offers significant area-and energy-savings. The synthesis results show remarkable improvements in the MRSU Dadda 4–2 architecture, which achieves 14.35× more energy-savings for 8 bits, 4.87× for 16 bits, and 2.22× for 32 bits compared to the multiplier unit automatically selected by the logic-synthesis tool. Furthermore, compared to the Booth multiplier with the Dadda compression tree, MRSU Dadda 4–2 exhibits 1.67× more energy-savings for 8 bits, 1.93× for 16 bits, and 1.95× for 32 bits.

关键词： Image coding Power demand Focusing Digital signal processing Computer architecture Very large scale integration Energy efficiency electronic circuits Adders Arithmetic

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