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Contract-Inspired Contest Theory for Controllable Image Generation in Mobile Edge Metaverse

IEEE Transactions on Mobile computing 2025年

作者： Liu, Guangyuan Du, Hongyang Wang, Jiacheng Niyato, Dusit Kim, Dong In Nanyang Technological University College of Computing and Data Science Energy Research Institute @ NTU Interdisciplinary Graduate Program Singapore University of Hong Kong Department of Electrical and Electronic Engineering Hong Kong Hong Kong Nanyang Technological University College of Computing and Data Science Singapore Sungkyunkwan University Department of Electrical and Computer Engineering Korea Republic of

The rapid advancement of immersive technologies has propelled the development of the Metaverse, where the convergence of virtual and physical realities necessitates the generation of high-quality, photorealistic images to enhance user experience. However, generating these images, especially through Generative Diffusion Models (GDMs), in mobile edge computing environments presents significant challenges due to the limited computing resources of edge devices and the dynamic nature of wireless networks. This paper proposes a novel framework that integrates contract-inspired contest theory, Deep Reinforcement Learning (DRL), and GDMs to optimize image generation in these resource-constrained environments. The framework addresses the critical challenges of resource allocation and semantic data transmission quality by incentivizing edge devices to efficiently transmit high-quality semantic data, which is essential for creating realistic and immersive images. The use of contest and contract theory ensures that edge devices are motivated to allocate resources effectively, while DRL dynamically adjusts to network conditions, optimizing the overall image generation process. Experimental results demonstrate that the proposed approach not only improves the quality of generated images but also achieves superior convergence speed and stability compared to traditional methods. This makes the framework particularly effective for optimizing complex resource allocation tasks in mobile edge Metaverse applications, offering enhanced performance and efficiency in creating immersive virtual environments. © 2002-2012 IEEE.

关键词： Resource allocation

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New Energy-Efficient 3-2 and 4-2 Approximate Adder Compressors Topologies

New Energy-Efficient 3-2 and 4-2 Approximate Adder Compresso...

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IEEE International Conference on electronics, Circuits and Systems (ICECS)

作者： Rodrigo Lopes Leonardo Antonietti Morgana M. A. Rosa Eduardo Costa Rafael Soares Sergio Bampi Graduate Program on Computing Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil PPGC & PGMICRO - Informatics Institute Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

Addition units are present across many computational kernels inherent in various error-tolerant applications, including machine learning, signal, image, and video processing. Notably, adder compressors are the target when high speed and low power are the main design concerns. This work introduces energy-efficient structures of 3-2 approximate adder compressors (Ax3-2) and three distinct versions of 4-2 approximate adder compressors (Ax4-2). We compared our proposed Ax3-2 and Ax4-2 compressors with state-of-the-art energy-efficient approximate adder compressors (AxACs). Both Ax3-2 and Ax4-2 models passed through rigorous tests as standalone units. Furthermore, we integrated the Ax4-2 models into an essential application kernel appearing in video coding, i.e., the Sum Squared Differences (SSD) video accelerator. We introduce Ax3-2 and Ax4-2 that yield a new Pareto front concerning both energy-quality and area-quality trade-offs, thereby demonstrating a marked improvement over the prevailing state-of-the-art energy-efficient AxACs.

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An Ultra Low-Energy VLSI Approximate Discrete Haar Wavelet Transform for ECG Data Compression

An Ultra Low-Energy VLSI Approximate Discrete Haar Wavelet T...

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IEEE International Conference on electronics, Circuits and Systems (ICECS)

作者： Arthur Cardozo Morgana M. A. Rosa Rafael Soares Eduardo Costa Sergio Bampi Graduate Program on Computing Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil PPGC & PGMICRO - Informatics Institute Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

This work proposes an ultra-low-energy ECG data compression with VLSI DHWT-based (discrete Haar wavelet transform) architecture to enable storage and transmission in resource-constrained environments. We present original, pruned, and approximate DHWT (ODHWT, PDHWT, and AxDHWT, respectively) hardware architectures for ECG data compression at ultra-high energy efficiency. Our best proposal employing the AxDHWT hardware architecture requires just five additions only. Using a PDHWT technique to improve energy efficiency observes the evolution of the signal-to-noise ratio and the ultimate impact on the ECG data compression application. The DHWT-based configurations architecture proposal achieves a minimum compression ratio of 0.125 (i.e., 1/8) and a PRD (percent root difference) <1.34. We implemented the VLSI architectures in 65nm CMOS technology in maximum and fixed frequencies and two different supply voltages. The AxDHWT occupies a die area of 0.64mm 2 . The measured total power is $0.534\mu {\mathrm {W}}$, the higher energy-savings among the ECG data compression architectures.

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Accuracy-, Delay- and Area-Driven Evaluation of Lower-Part Approximate Parallel Prefix Adder

Accuracy-, Delay- and Area-Driven Evaluation of Lower-Part A...

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IEEE International Conference on electronics, Circuits and Systems (ICECS)

作者： Morgana M. A. Rosa Eduardo Costa Rafael Soares Sergio Bampi Graduate Program on Computing Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil PPGC & PGMICRO - Informatics Institute Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

This work proposes an accuracy-driven evaluation model of an approximate adder (AxA) called an approximate parallel prefix adder (AxPPA). It explores the significance of approximate computing (AxC) in optimizing performance and energy efficiency in computer systems by accepting minor accuracy trade-offs. We examine the AxPPA through a meticulous error analysis model and an automated analysis framework that comprehensively evaluates area and delay based on the fundamental equations of parallel prefix adders (PPAs). Additionally, it emphasizes the importance of lower-part approximation in adders, effectively addressing the elongation of carry chains and enhancing overall efficiency. The choice of approximation method directly impacts computational accuracy, resulting in variations in the number of approximated bits and carry chain length for a given tolerance level. Conducting a thorough comparison of accuracy trade-offs requires a unique design and simulation for each unit and approximation level, which can be time-consuming, particularly in larger circuits. Therefore, the proposed approach facilitates the exploration of larger circuit design space encompassing multiple AxAs, significantly minimizing time investment. In our experiments, the accuracy-driven evaluation of the lower part approximation method in AxA took 71.268 milliseconds for 1 million random inputs, with a K -bits approximation ranging from 1 to 16. The results indicate that AxPPA exhibits a minor error magnitude among the explored literature AxAs, being approximately 50.97% more accurate on average.

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Architectural Exploration for Energy-Efficient LMS and NLMS Adaptive Filters VLSI Design

Architectural Exploration for Energy-Efficient LMS and NLMS ...

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Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)

作者： Pedro T. L. Pereira Guilherme Paim Eduardo Costa Paulo Flores Sergio Bampi Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Brazil INESC-ID Instituto Superior Técnico ULisboa Portugal

Adaptive filtering plays an essential role in digital signal processing (DSP), being present in many application fields such as noise reduction, telecommunication, and audio signal processing. Notably, the least mean square (LMS) and its normalized version (NLMS) are the most used algorithms due to their simplicity and robustness, which turn them attractive to hardware solutions. This work proposes architectural solutions for LMS and NLMS algorithms targeting an energy-efficient VLSI design. We explore fully sequential, fully parallel, and semi-parallel architectures reusing the hardware as much as possible for both algorithms. It allows for investigating the number of steps necessary for each architecture, demonstrating the energy per operation, circuit area, and throughput savings. The synthesis results highlight the semi-parallel architectures LMS-2 steps and NLMS-3 steps have the best trade-off energy-speed. In addition, we proved the architecture’s energy efficiency in a harmonic canceling case study, achieving more than 60% in energy savings using both filters.

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AxASRE: A Novel Approach to Approximate Adder Synthesis Results Estimation.

AxASRE: A Novel Approach to Approximate Adder Synthesis Resu...

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International Conference on Dependable Systems and Networks Workshops (DSN-W)

作者： Pedro T. L. Pereira Guilherme Paim Paulo Flores Eduardo Costa Sergio Bampi Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Brazil INESC-ID Instituto Superior Técnico ULisboa Portugal Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Brazil

Thanks to the high energy efficiency achieved by approximate circuits, the exploration of approximate solutions for a wide of applications is the focus of academic and industrial research. However, defining the most appropriate approximation considering the power consumption and accuracy trade-off can be exhaustive. This paper proposes a novel approach to estimate the synthesis results for approximate adders (AxA) with different bit-width and approximation levels based on a database and simple mathematical operations to reduce the synthesis process complexity during an approximate circuit development. We implement the proposed approach to estimate the synthesis results for the Copy, Error-Tolerant Adder I (ETA-I), Lower-part-or (LOA), and Truncation (Trunc) AxAs. Comparing our estimation with real synthesis results obtained by an industrial synthesis tool, we prove the approach’s efficiency by presenting an average error on the estimated parameters (area, power and delay) less than 10% in the worst case. In addition, our approach reduces by more than 25 times the number of synthesis runs when estimating the synthesis results for all circuits in the bit width range of 2 to 64 with all possible approximation levels.

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Lightweight Authenticated Key Agreement Protocol for Smart Power Grid Systems Using PUF

IEEE Open Journal of the Communications Society

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IEEE Open Journal of the Communications Society 2024年 5卷 3568-3580页

作者： Zahoor, Amina Mahmood, Khalid Saleem, Muhammad Asad Badar, Hafiz Muhammad Sanaullah Le, Tuan-Vinh Das, Ashok Kumar Department of Computer Science Sahiwal57000 Pakistan National Yunlin University of Science and Technology Graduate School of Intelligent Data Science Douliu64002 Taiwan University of Electronic Science and Technology of China School of Computer Science and Engineering Chengdu611731 China Emerson University Multan Department of Emerging Computing Technologies Multan61000 Pakistan Fu Jen Catholic University Bachelor's Program of Artificial Intelligence and Information Security New Taipei City24206 Taiwan International Institute of Information Technology Hyderabad Center for Security Theory and Algorithmic Research Hyderabad500032 India

The Smart Power Grid (SPG) is pivotal in orchestrating and managing demand response in contemporary smart cities, leveraging the prowess of Information and Communication Technologies (ICTs). Within the immersive SPG environment, the ubiquitous deployment of smart meters stands as a testament to their paramount importance in the realm of vigilant monitoring and oversight. These smart meters are installed on high-tension electricity lines and transmit information about electricity outages and other issues to the utility center. To access services from utility centers, smart meters need to communicate securely over a public channel, even though the network itself is insecure. However, potential attacks from adversaries ( Ad) can exploit this communication. Therefore, protecting this communication is of utmost importance. Several privacy-preserving authentication protocols designed for SPG have been introduced in the literature. Nevertheless, a significant number of these protocols exhibit vulnerabilities to diverse security attacks. This article introduces a lightweight and anonymous authentication protocol specifically designed to address these concerns in the SPG environment. Our protocol ensures both security and efficiency, surpassing other comparable protocols in terms of its lightweight nature. By employing both formal and informal analysis, we showcase the robustness of our protocol against significant attacks while remaining lightweight. The proposed protocol provides added security features and incurs 23.8879% lower computation cost than related protocols. Consequently, our protocol is highly suitable for implementation in the SPG system. © 2020 IEEE.

关键词： Hash functions

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Contract-Inspired Contest Theory for Controllable Image Generation in Mobile Edge Metaverse

arXiv

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arXiv 2025年

作者： Liu, Guangyuan Du, Hongyang Wang, Jiacheng Niyato, Dusit Kim, Dong In College of Computing and Data Science The Energy Research Institute @ NTU Interdisciplinary Graduate Program Nanyang Technological University Singapore Department of Electrical and Electronic Engineering University of Hong Kong Hong Kong College of Computing and Data Science Nanyang Technological University Singapore Department of Electrical and Computer Engineering Sungkyunkwan University Korea Republic of

关键词： Mobile edge computing

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Energy-Efficient Haar Transform Architectures Using Efficient Addition Schemes 11

Energy-Efficient Haar Transform Architectures Using Efficien...

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11th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2020

作者： Seidel, Henrique Rosa, Morgana Da Paim, Guilherme Costa, Eduardo Da Almeida, Sergio Bampi, Sergio Graduate Program on Electronic Engineering and Computing Pelotas Brazil Porto Alegre Brazil

ISBN: (纸本)9781728134277

This paper proposes an energy-efficient Haar transform architecture using efficient adders circuits. Nine levels of decomposition in a fixed-point format are used in the architectures. The Processing Module (PM) of Haar explores efficient Parallel Prefix Adders (PPA) and adder compressors. Since power-of-two operations approximate one of the inputs of the PM module, efficient adder compressors implement them. It allowed a very high precision adjustment of the transform coefficient. The architectures were described in VHDL and synthesized using the ST 65nm CMOS cell library. The results show that the Haar architecture with 4-2 and 5-2 compressors in the PM module, both with the recombination line with a Sklansky (SK) adder, is more efficient. It has a reduction of 33.6% in the cell area, with a 35.7% reduction in total power in comparison with the literature. Moreover, the Haar architecture with 4-2 and 5-2 adder compressors is more efficient than the one using the tool-selected implementation of the behavioral "+" (sum) in VHDL, with 23% of power reduction. © 2020 IEEE.

关键词： Adders

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A Multiplier-Less Level-3 Haar Wavelet Transform Approximation Requiring Five Additions Only

A Multiplier-Less Level-3 Haar Wavelet Transform Approximati...

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Proceedings of the IEEE Dallas Circuits and Systems Workshop (DCAS)

作者： Morgana M. A. Da Rosa Guilherme Paim Henrique B. Seidel Sé rgio Almeida Eduardo A. C. Da Costa Sergio Bampi Graduate Program on Electronic Engineering and Computing Universidade Cat&#x00F3 lica de Pelotas (UCPel) Brazil Graduate Program in Microelectronics (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Brazil

ISBN: (数字)9781665498852

ISBN: (纸本)9781665498869

Approximate transform kernels have emerged as an alternative design to reduce the hardware complexity of digital signal processors by exploiting the intrinsic error resilience of many embedded consumer electronics applications such as signal, image and video processing, and computer vision. The approximate level-4 Haar wavelet transform (AxHWT-4) is the state-of-the-art approximate transform for ECG (electrocardiogram) signal processing and reduces more than nine times the energy consumption compared to the exact transform. In this work, we propose an approximate level-3 Haar wavelet transform (AxHWT-3) for increasing the hardware design efficiency with related to the AxHWT-4 while obtaining higher R-peak detection accuracy in the electrocardiogram signal. Our AxHWT-3 approximation is performed in the Haar matrix kernel to eliminate its multiplications which in the hardware design results in savings of energy consumption and VLSI hardware area. Our AxHWT3 proposal achieves an R-peak detection accuracy of more than 99% and reduces the energy consumption by 15.98 times and the VLSI area by 12.64 times compared to the exact solution (i.e., the original level-3 Haar). In addition, the proposed AxHWT3 outperforms the state-of-the-art AxHWT-4 with a savings of about 32% in power dissipation and 19.5% in VLSI area.

关键词： Wavelet transforms Energy consumption Computer architecture Very large scale integration Electrocardiography Signal processing Hardware

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