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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Thomas V. Fontanari Guilherme Paim Leandro M. G. Rocha Patrícia Ücker Eduardo Costa Sergio Bampi Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9781728134277

ISBN: (纸本)9781728134284

Adder compressors (AC) have been extensively used in digital circuits like multipliers and transforms where several multi-bit operands have to be summed in parallel. Most available AC structures on the literature do not handle efficiently the intermediary carry propagation on wider bit-widths, potentially leading to longer critical paths and higher energy consumption. Hence, this paper proposes a novel non-hierarchical 8-2 adder compressor CMOS design with limited and constant carry propagation path for N-bit operands, minimizing both circuit delay and power dissipation. The proposed architecture as well as the state-of-the-art ACs are synthesized in a 65 nm CMOS commercial standard cell library, for multiple operands bit-widths. Logic synthesis results show that our proposed design reaches a maximum operating frequency at least 15.2% higher than current state-fo-th-art ACs, while also achieving up to 13.6% of power dissipation savings, increasing the savings with the bitwidth.

关键词： Adders Power dissipation Computer architecture Logic gates Proposals Propagation delay Transforms

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programming Variational Quantum Circuits with Quantum-Train Agent

Programming Variational Quantum Circuits with Quantum-Train ...

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Quantum Communications, Networking, and computing (QCNC), International Conference on

作者： Chen-Yu Liu Samuel Yen-Chi Chen Kuan-Cheng Chen Wei-Jia Huang Yen-Jui Chang Graduate Institute of Applied Physics National Taiwan University Taipei Taiwan Hon Hai (Foxconn) Research Institute Taipei Taiwan Wells Fargo New York NY USA Department of Electrical and Electronic Engineering Imperial College London London UK Centre for Quantum Engineering Science and Technology (QuEST) Imperial College London London UK Quantum Information Center Chung Yuan Christian University Taoyuan City Taiwan Master Program in Intelligent Computing and Big Data Chung Yuan Christian University Taoyuan City Taiwan

ISBN: (数字)9798331531591

ISBN: (纸本)9798331531607

This study introduces the Quantum-Train Quantum Fast Weight programmer (QT-QFWP) framework, enabling efficient and scalable programming of variational quantum circuits (VQCs) through quantum-driven parameter updates for the classical slow programmer controlling the fast programmer VQC. By optimizing quantum and classical parameter management, QT-QFWP significantly reduces parameters (by 70–90%) compared to Quantum Long Short-Term Memory (QLSTM) and Quantum Fast Weight programmer (QFWP) while maintaining accuracy. Benchmarking on time-series tasks—including Damped Simple Harmonic Motion (SHM), NARMA5, and Simulated Gravitational Waves (GW)—demonstrates superior efficiency and predictive accuracy. QT-QFWP is particularly advantageous for near-term quantum systems, addressing qubit and gate fidelity constraints, enhancing VQC deployment in time-sensitive applications, and expanding quantum computing’s role in machine learning.

关键词： Quantum system Accuracy Computational modeling Qubit Neural networks programming Predictive models Quantum circuit Physics Long short term memory

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programming Variational Quantum Circuits with Quantum-Train Agent

arXiv

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arXiv 2024年

作者： Liu, Chen-Yu Chen, Samuel Yen-Chi Chen, Kuan-Cheng Huang, Wei-Jia Chang, Yen-Jui Graduate Institute of Applied Physics National Taiwan University Taipei Taiwan Research Institute Taipei Taiwan Wells Fargo New YorkNY United States Department of Electrical and Electronic Engineering Imperial College London London United Kingdom Imperial College London London United Kingdom Quantum Information Center Chung Yuan Christian University Taoyuan City Taiwan Master Program in Intelligent Computing and Big Data Chung Yuan Christian University Taoyuan City Taiwan

In this study, the Quantum-Train Quantum Fast Weight programmer (QT-QFWP) framework is proposed, which facilitates the efficient and scalable programming of variational quantum circuits (VQCs) by leveraging quantum-driven parameter updates for the classical slow programmer that controls the fast programmer VQC model. This approach offers a significant advantage over conventional hybrid quantum-classical models by optimizing both quantum and classical parameter management. The framework has been benchmarked across several time-series prediction tasks, including Damped Simple Harmonic Motion (SHM), NARMA5, and Simulated Gravitational Waves (GW), demonstrating its ability to reduce parameters by roughly 70-90% compared to Quantum Long Short-term Memory (QLSTM) and Quantum Fast Weight programmer (QFWP) without compromising accuracy. The results show that QT-QFWP outperforms related models in both efficiency and predictive accuracy, providing a pathway toward more practical and cost-effective quantum machine learning applications. This innovation is particularly promising for near-term quantum systems, where limited qubit resources and gate fidelities pose significant constraints on model complexity. QT-QFWP enhances the feasibility of deploying VQCs in time-sensitive applications and broadens the scope of quantum computing in machine learning domains. Copyright © 2024, The Authors. All rights reserved.

关键词： Long short-term memory

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Exploring NLMS and IPNLMS Adaptive Filtering VLSI Hardware Architectures for Robust EEG Signal Artifacts Elimination

Exploring NLMS and IPNLMS Adaptive Filtering VLSI Hardware A...

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IEEE International Conference on electronics, Circuits and Systems (ICECS)

作者： Andrei La Rosa Patrícia Ucker Guilherme Paim Eduardo da Costa Sérgio Almeida Sergio Bampi Graduate Program on Computing Federal University of Pelotas (UFPel) Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Brazil Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Brazil

ISBN: (数字)9781728160443

ISBN: (纸本)9781728160450

The elimination of artifacts is a crucial procedure to extract the full potential of the information into the EEG processing. Embedded systems require low circuit area (cost) and efficient hardware architectures. Adaptive filtering plays a vital role as a single method and hybrid approaches for robustly eliminating the noise of the real-world EEG measures. In this paper, we propose and implement hardware architectures for both NLMS and IPNLMS adaptive filters. We investigate the filtering performance and circuit area, timing, and power dissipation of the hardware architecture proposals. To leverage the power-efficiency, we improve our hardware architectures employing the data-gating circuit design technique, which provided up to 20% power savings. Also, applying an HDL-Simulink co-simulation, we perform the hardware architectures tradeoff comparing the synthesis results and filtering performance. Our investigation demonstrates that IPNLMS reduces the time domain error in 11%, increasing less than 1% of circuit area and about the double of the energy per operation, compared to the NLMS.

关键词： Electroencephalography Hardware Computer architecture Convergence Measurement Clocks Proposals

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Combining m=2 Multipliers and Adder Compressors for Power Efficient Radix-4 Butterfly

Combining m=2 Multipliers and Adder Compressors for Power Ef...

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Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Guilherme Ferreira Leandro M. G. Rocha Eduardo Costa Sergio Bampi Graduate Program in Microelectronics (PGMICRO) - Federal University of Rio Grande do Sul (UFRGS) Brazil Graduate Program in Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Brazil

ISBN: (数字)9781728180588

ISBN: (纸本)9781728180595

In this work, we propose a power-efficient hardware architecture for 16-bit m Radix-4 DIT (Decimation in Time) butterfly using radix-2 m multipliers, with m=2, and 4-2 adder compressors. The multiplier uses both Wallace and Dadda schemes in the addition tree, with Carry-Select, Kogge Stone, and '+' operator from the tool internally. We used a method for a realistic power extraction with the standard delay format. The results show that our best-proposed Radix-4 butterfly saves up to 25% of power dissipation when compared with the original Radix-4 butterfly using the synthesis tool operators for both adders and multipliers. The optimized structure combines the m=2 Wallace-based multiplier, employing Kogge-Stone adder into its addition tree, and 4-2 adder compressors.

关键词： Adders Compressors Tools Computer architecture Power dissipation Capacitance Libraries

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Optimizing Iterative-based Dividers for an Efficient Natural Logarithm Operator Design

Optimizing Iterative-based Dividers for an Efficient Natural...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Patrícia Ücker Miguel R. Weirich Guilherme Paim Eduardo A. C. da Costa Sergio Bampi Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Brazil Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Brazil

ISBN: (数字)9781728134277

ISBN: (纸本)9781728134284

This work proposes to optimize iterative-based dividers for a natural logarithm operator design. The logarithm operator approximates the function at the base e. Such an operator is implemented using Taylor Series approximation. In this approximation, the division is a costly operation. In this work, we explore two iterative-based divider circuits for logarithm operator. We also offer an algorithm responsible for allowing input values different from the ones in the convergence region of the Taylor Series, with a reduced number of iterations. Through co-simulation using both the Matlab ® and ModelSim ® softwares, it was possible to determine the approximation quality of the implemented circuits, with a curve response very close to the Matlab one. Moreover, the Goldschmidt divider presents a slightly fewer relative error, mainly for higher input values comparing with Newton-Raphson. Synthesis results show that although the logarithm circuit with Newton-Raphson divider has marginally more area, it is more power-efficient than the one using Goldschmidt divider.

关键词： Approximation algorithms Taylor series Mathematical model Newton method Convergence Hardware Matlab

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An Efficient NLMS-based VLSI Architecture for Robust FECG Extraction and FHR Processing

An Efficient NLMS-based VLSI Architecture for Robust FECG Ex...

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IEEE International Conference on electronics, Circuits and Systems (ICECS)

作者： Patrícia U. L. da Costa Guilherme Paim Leandro Rocha Eduardo da Costa Sérgio Almeida Sergio Bampi Graduate Program on Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Brazil Graduate Program on Microelectronics (PGMicro) - Federal University of Rio Grande do Sul (UFRGS) Brazil

ISBN: (数字)9781728160443

ISBN: (纸本)9781728160450

This work presents an efficient NLMS-based VLSI architecture to extract the fetal electrocardiogram (FECG) and detect the fetal heart rate (FHR), using the adaptive filter strategy. The efficient NLMS-based architecture herein investigated can robustly cancel the high-noised mother-related ECG signals, enabling the FHR measurement. We used the Improved Fetal Pan and Tompkins Algorithm (IFPTA) to detect fetal R-peak and calculate the FHR. Our NLMS-based VLSI architecture effectively detects the R-peaks in the extracted FECG with 93.2% accuracy with the only 2.4 mW of total power dissipation.

关键词： Fetal heart rate Very large scale integration Computer architecture Electrocardiography Hardware Thorax Power dissipation

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The Radix-2m Squared Multiplier

The Radix-2m Squared Multiplier

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IEEE International Conference on electronics, Circuits and Systems (ICECS)

作者： Morgana M. A. da Rosa Guilherme Paim Leandro M. G. Rocha Eduardo A. C. da Costa Sergio Bampi Graduate Program on Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil Graduate Program on Microelectronics (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9781728160443

ISBN: (纸本)9781728160450

Multipliers are present in a large variety of applications. However, it is usually responsible for most of the power dissipation. On the other hand, the squared multiplier is a particular case of the general-purpose multiplier, in which both operands are the same, proportioning many architecture optimizations. This paper introduces the radix-2 m squared array multiplier architecture. Our architecture proposal for the squared multiplier is the first to reduces the partial products by splitting the operands into mbit groups. Our squared multiplier architecture explores different adder schemes in the multipliers adder tree. As a case study, we demonstrate our squared multiplier proposal for m=2 (radix-4). We investigated the Wallace and Dadda addition trees employing as final carry propagating adder (CPA) the Ripple Carry adder (RCA) and with the adder automatically selected by the synthesis tool. Our best radix-4 squared multiplier proposal employs the Dadda technique and the RCA to implement the adder tree, showing significant energy savings of 20.5%, 56.5%, and 47.4%, for 8, 16, and 32 bits, respectively, compared to the squared multiplier automatically selected by the synthesis tool. Furthermore, our best radix-4 squared multiplier proposal outperforms the Vedic squared multiplier with energy savings in about 21.5%, 71.0%, and 9.0%, respectively, for 8, 16, and 32 bits.

关键词： Adders Tools Proposals Vegetation Computer architecture Optimization Logic gates

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Exploring Efficient Adder Compressors for Power-Efficient Sum of Squared Differences Design

Exploring Efficient Adder Compressors for Power-Efficient Su...

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IEEE International Conference on electronics, Circuits and Systems (ICECS)

作者： Morgana M. A. da Rosa Guilherme Paim Leandro M.G. Rocha Eduardo A.C. da Costa Sergio Bampi Graduate Program on Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9781728160443

ISBN: (纸本)9781728160450

This work explores the 8-2 adder compressor in the addition tree of the Sum of Squared Differences (SSD) architecture. SSD is a distortion metric of the motion estimation in the High-Efficiency Video Coding (HEVC) standard. Distortion metrics are the most time-consuming operations of the encoder. SSD hardware architecture consists of a sum tree that accumulates the calculation of the partial values. The addition tree in the SSD opens an opportunity of exploring efficient addition schemes such as the combinations of efficient adder compressors. The SSD architectures herein presented are compared regarding power dissipation using real video sequences. Our work overcomes the state-of-the-art related work which they investigated different SSD hardware architectures concluding that employing the synthesis tool arithmetic operators are the best choice to reduce the power dissipation. According to our results, we reveal that the SSD employing the 8-2 hierarchical adder compressor combined with a Brent-Kung adder in the final sum saves on average 29.4 % of total power dissipation, when comparing with SSD implemented using the arithmetic operators automatically selected by the synthesis tool.

关键词： Compressors Adders Logic gates Computer architecture Tools Measurement Distortion

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Energy-Efficient Haar Transform Architectures Using Efficient Addition Schemes

Energy-Efficient Haar Transform Architectures Using Efficien...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Henrique Seidel Morgana da Rosa Guilherme Paim Eduardo da Costa Sergio Almeida Sergio Bampi Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9781728134277

ISBN: (纸本)9781728134284

This paper proposes an energy-efficient Haar transform architecture using efficient adders circuits. Nine levels of decomposition in a fixed-point format are used in the architectures. The Processing Module (PM) of Haar explores efficient Parallel Prefix Adders (PPA) and adder compressors. Since power-of-two operations approximate one of the inputs of the PM module, efficient adder compressors implement them. It allowed a very high precision adjustment of the transform coefficient. The architectures were described in VHDL and synthesized using the ST 65nm CMOS cell library. The results show that the Haar architecture with 4-2 and 5-2 compressors in the PM module, both with the recombination line with a Sklansky (SK) adder, is more efficient. It has a reduction of 33.6% in the cell area, with a 35.7% reduction in total power in comparison with the literature. Moreover, the Haar architecture with 4-2 and 5-2 adder compressors is more efficient than the one using the tool-selected implementation of the behavioral "+" (sum) in VHDL, with 23% of power reduction.

关键词： Adders Compressors Computer architecture Discrete wavelet transforms Microprocessors

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