This work presents an efficient NLMS-based VLSI architecture to extract the fetal electrocardiogram (FECG) and detect the fetal heart rate (FHR), using the adaptive filter strategy. The efficient NLMS-based architectu...
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ISBN:
(数字)9781728160443
ISBN:
(纸本)9781728160450
This work presents an efficient NLMS-based VLSI architecture to extract the fetal electrocardiogram (FECG) and detect the fetal heart rate (FHR), using the adaptive filter strategy. The efficient NLMS-based architecture herein investigated can robustly cancel the high-noised mother-related ECG signals, enabling the FHR measurement. We used the Improved Fetal Pan and Tompkins Algorithm (IFPTA) to detect fetal R-peak and calculate the FHR. Our NLMS-based VLSI architecture effectively detects the R-peaks in the extracted FECG with 93.2% accuracy with the only 2.4 mW of total power dissipation.
This paper proposes an energy-efficient Haar transform architecture using efficient adders circuits. Nine levels of decomposition in a fixed-point format are used in the architectures. The Processing Module (PM) of Ha...
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ISBN:
(数字)9781728134277
ISBN:
(纸本)9781728134284
This paper proposes an energy-efficient Haar transform architecture using efficient adders circuits. Nine levels of decomposition in a fixed-point format are used in the architectures. The Processing Module (PM) of Haar explores efficient Parallel Prefix Adders (PPA) and adder compressors. Since power-of-two operations approximate one of the inputs of the PM module, efficient adder compressors implement them. It allowed a very high precision adjustment of the transform coefficient. The architectures were described in VHDL and synthesized using the ST 65nm CMOS cell library. The results show that the Haar architecture with 4-2 and 5-2 compressors in the PM module, both with the recombination line with a Sklansky (SK) adder, is more efficient. It has a reduction of 33.6% in the cell area, with a 35.7% reduction in total power in comparison with the literature. Moreover, the Haar architecture with 4-2 and 5-2 adder compressors is more efficient than the one using the tool-selected implementation of the behavioral "+" (sum) in VHDL, with 23% of power reduction.
Multipliers are present in a large variety of applications. However, it is usually responsible for most of the power dissipation. On the other hand, the squared multiplier is a particular case of the general-purpose m...
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ISBN:
(数字)9781728160443
ISBN:
(纸本)9781728160450
Multipliers are present in a large variety of applications. However, it is usually responsible for most of the power dissipation. On the other hand, the squared multiplier is a particular case of the general-purpose multiplier, in which both operands are the same, proportioning many architecture optimizations. This paper introduces the radix-2 m squared array multiplier architecture. Our architecture proposal for the squared multiplier is the first to reduces the partial products by splitting the operands into mbit groups. Our squared multiplier architecture explores different adder schemes in the multipliers adder tree. As a case study, we demonstrate our squared multiplier proposal for m=2 (radix-4). We investigated the Wallace and Dadda addition trees employing as final carry propagating adder (CPA) the Ripple Carry adder (RCA) and with the adder automatically selected by the synthesis tool. Our best radix-4 squared multiplier proposal employs the Dadda technique and the RCA to implement the adder tree, showing significant energy savings of 20.5%, 56.5%, and 47.4%, for 8, 16, and 32 bits, respectively, compared to the squared multiplier automatically selected by the synthesis tool. Furthermore, our best radix-4 squared multiplier proposal outperforms the Vedic squared multiplier with energy savings in about 21.5%, 71.0%, and 9.0%, respectively, for 8, 16, and 32 bits.
This work explores the 8-2 adder compressor in the addition tree of the Sum of Squared Differences (SSD) architecture. SSD is a distortion metric of the motion estimation in the High-Efficiency Video Coding (HEVC) sta...
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ISBN:
(数字)9781728160443
ISBN:
(纸本)9781728160450
This work explores the 8-2 adder compressor in the addition tree of the Sum of Squared Differences (SSD) architecture. SSD is a distortion metric of the motion estimation in the High-Efficiency Video Coding (HEVC) standard. Distortion metrics are the most time-consuming operations of the encoder. SSD hardware architecture consists of a sum tree that accumulates the calculation of the partial values. The addition tree in the SSD opens an opportunity of exploring efficient addition schemes such as the combinations of efficient adder compressors. The SSD architectures herein presented are compared regarding power dissipation using real video sequences. Our work overcomes the state-of-the-art related work which they investigated different SSD hardware architectures concluding that employing the synthesis tool arithmetic operators are the best choice to reduce the power dissipation. According to our results, we reveal that the SSD employing the 8-2 hierarchical adder compressor combined with a Brent-Kung adder in the final sum saves on average 29.4 % of total power dissipation, when comparing with SSD implemented using the arithmetic operators automatically selected by the synthesis tool.
Arithmetic operations are intrinsic to any embedded devices, and they usually have a significant impact on the circuit speed, area, and power consumption. Applications like video processing, digital signal processing,...
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ISBN:
(数字)9781728170442
ISBN:
(纸本)9781728170459
Arithmetic operations are intrinsic to any embedded devices, and they usually have a significant impact on the circuit speed, area, and power consumption. Applications like video processing, digital signal processing, machine learning, among others, rely heavily on multipliers to execute their algorithms. Radix-2 m multipliers have been reported as one of the most power-efficient circuits. However, their architecture has not been explored nor optimized to improve the circuit quality. This work proposed two sign extension optimization techniques for these multipliers, aiming for better power efficiency and a smaller area. The baseline radix-4 (m=2) multiplier and its optimized versions were synthesized in a commercial 65nm technology to evaluate their performance. Results show that the optimized versions achieve power efficiency gains from 16.4% up to 78.6%, with circuit area reduction up to 49.2%.
Cryptography hardware design is a key challenge towards the confidentiality advance in the prominent field of the internet of things (IoT). The rise of IoT embedded devices boosts the demand for power- and area- effic...
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ISBN:
(数字)9781728180588
ISBN:
(纸本)9781728180595
Cryptography hardware design is a key challenge towards the confidentiality advance in the prominent field of the internet of things (IoT). The rise of IoT embedded devices boosts the demand for power- and area- efficient solutions for cryptography hardware. The higher the robustness of the cryptography algorithm is, the higher are the hardware complexity, the circuit area, and energy consumption. Asymmetric algorithms are a particular class widely employed in ultra-secure cryptosystems. The high time-hardness to break the private-key in asymmetric algorithms is a result of its high mathematical complexity. RSA is an asymmetric algorithm that performs successive modular multiplications to encrypt and de-encrypt the information. Therefore, arithmetic operators are the most significant part regarding circuit area and power dissipation. This work evaluates a design space exploration for power- and area-efficient hardware VLSI design in the modular Montgomery multiplier employed in the RSA algorithm.
This paper introduces CompressedMediQ, a novel hybrid quantum-classical machine learning pipeline specifically developed to address the computational challenges associated with high-dimensional multi-class neuroimagin...
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This paper introduces CompressedMediQ, a novel hybrid quantum-classical machine learning pipeline specifically developed to address the computational challenges associated with high-dimensional multi-class neuroimagin...
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ISBN:
(数字)9798331519315
ISBN:
(纸本)9798331519322
This paper introduces CompressedMediQ, a novel hybrid quantum-classical machine learning pipeline specifically developed to address the computational challenges associated with high-dimensional multi-class neuroimaging data analysis. Standard neuroimaging datasets, such as large-scale MRI data from the Alzheimer’s Disease Neuroimaging Initiative and Neuroimaging in Frontotemporal Dementia, present significant hurdles due to their vast size and complexity. CompressedMediQ integrates classical HPC nodes for advanced MRI pre-processing and Convolutional Neural Network (CNN)-PCA-based feature extraction and reduction, addressing the limited-qubit availability for quantum data encoding in the NISQ era. This is followed by Quantum Support Vector Machine (QSVM) classification. By utilizing quantum kernel methods, the pipeline optimizes feature mapping and classification, enhancing data separability and outperforming traditional neuroimaging analysis techniques. Experimental results highlight the pipeline’s superior accuracy in dementia staging, validating the practical use of quantum machine learning in clinical diagnostics. Despite the limitations of NISQ devices, this proof-of-concept demonstrates the transformative potential of quantum-enhanced learning, paving the way for scalable and precise diagnostic tools in healthcare and signal processing.
This paper brings out a structured methodology for identifying intervals of communication time-delay where consensus in directed networks of multiple agents with high-order integrator dynamics is achieved. It is built...
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This paper brings out a structured methodology for identifying intervals of communication time-delay where consensus in directed networks of multiple agents with high-order integrator dynamics is achieved. It is built upon the stability analysis of a transformed consensus problem which preserves all the nonzero eigenvalues of the Laplacian matrix of the associated communication topology graph. It is shown that networks of agents with first-order integrator dynamics can be brought to consensus independently of communication delay, on the other hand, for agents with second-order integrator dynamics, the consensus is achieved independently of communication delay only if certain conditions axe satisfied. Conversely, if such conditions axe not satisfied, it is shown how to compute the intervals of communication delay where multiple agents with second-order or higher-order can be brought to consensus. The paper is ended by showing an interesting example of a network of agents with second-order integrator dynamics which is consensable on the first time-delay interval, but as the time-delay increases, it loses consensability on the second time-delay interval, then it becomes consensable again on the third time-delay interval, and finally it does not achieve consensus any more on the fourth time-delay interval. This example shows the importance of analyzing consensus with time-delay in different intervals.
Sum of Absolute Transformed Differences (SATD) is a distortion metric based on the Hadamard Transform. It is used in current video encoders inside the refinement stage of motion estimation, which decides the best bloc...
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ISBN:
(数字)9781728134277
ISBN:
(纸本)9781728134284
Sum of Absolute Transformed Differences (SATD) is a distortion metric based on the Hadamard Transform. It is used in current video encoders inside the refinement stage of motion estimation, which decides the best block of pixels to be used as prediction for each block to be encoded. To reduce the computational effort incurred by the SATD calculation, this work proposes an approximate SATD hardware accelerator by excluding columns of adders/subtractors of the 8 × 8 Hadamard Transform (HT). The proposed approximate accelerator reduces energy by up to 40.78% compared to the precise SATD accelerator.
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