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IEEE Design and Test 2025年

作者： Ferreira, Állan F. G. Zilch, Lucas B. Lubaszewski, Marcelo S. Balen, Tiago R. Universidade Federal Do Rio Grande Do Sul Graduate Program in Microelectronics - PGMICRO Porto Alegre Brazil

This work introduces a machine learning method for indirect test pattern generation in analog and mixed-signal circuits. The proposed method employs a low-cost test generation tool to simulate circuit specifications and parametric measures, incorporating variability via Monte Carlo simulation. Learning models are trained to relate low-cost DC node measurements to circuit specifications, enabling indirect testing. Validation on a 180 nm fully-differential integrated filter achieved R2 scores of 0.76 for DC gain, 0.76 for cutoff frequency, and 0.98 for slew rate. A simulation fault injection campaign using a structural fault model (catastrophic and parametric faults) demonstrated 100% fault coverage with 19 measurements. © 2013 IEEE.

关键词： Mixed signal integrated circuits

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Energy-Efficient Hardware Architecture for VVC TZS Using Approximate Subtractors

Energy-Efficient Hardware Architecture for VVC TZS Using App...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Rafael Ferreira Luciano Agostini Cláudio M. Diniz Bruno Zatt Video Technology Research Group (ViTech) Graduate Program in Computing (PPGC) Federal University of Pelotas (UFPel) Pelotas RS Brazil Microelectronics Group (GME) Graduate Program in Microelectronics (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

This paper investigates the impact of approximate subtractors in the hardware architecture of the Sum of Absolute Differences (SAD) computation within the Test Zone Search (TZS) algorithm, commonly used in current video encoders like the Versatile Video Coding (VVC). Four state-of-the-art imprecise subtractors $(AppS, AXSC1, AXSC2, AXSC3)$ were analyzed across various video resolutions to assess their influence on computational effort, energy consumption, and coding efficiency. The results show that subtractors like $AppS_{4}$ and $AXCS1_{4}$ provide significant reductions in energy consumption with minimal impact on video coding quality. These findings are especially relevant for low-power devices and embedded systems, where energy efficiency is critical. The use of imprecise subtractors offers a promising tradeoff between computational efficiency and energy savings, making them a viable solution for high-performance video encoders.

关键词： Video coding Energy consumption Embedded systems Energy conservation Energy resolution Computer architecture Energy efficiency Hardware Computational efficiency Power dissipation

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Quality-Reconfigurable Approximate Multiplier Utilizing Select Leading One-Bit Blocks

Quality-Reconfigurable Approximate Multiplier Utilizing Sele...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： João M. Bedin Pedro T. L. Pereira Rodrigo N. Wuerdig Eduardo Da Costa Sergio Bampi Graduate Program in Microelectronics (PGMicro) - Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil Graduate Program in Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

Multipliers are essential for emerging technologies, as they are vital arithmetic circuits in many energy-efficient applications, such as digital signal processing and machine learning applications. Approximate multipliers (AxM) became an optimal option for applications in ASIC systems with error tolerance. This paper proposes to develop a run-time reconfigurable AxM with four approximation levels in a single circuit, evaluating accuracy and circuit metrics (e.g., circuit area, timing, and power consumption) based on the leading one-bit-based approximate (LoBA) multiplier. The results achieve a circuit area reduction of 52% less area and up to 27% less power consumption when compared with equivalent architecture based on LoBA state-of-art. Applying the proposed RLoBA to a normalized least mean square (NLMS) adaptive filter case study, we obtain 22.95% less power consumption using dynamic approximate level selection than the precise multiplier while maintaining the same accuracy level.

关键词： Measurement Power demand Accuracy Circuits Adaptive filters Machine learning Lead Timing Reconfigurable architectures Standards

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Exploring Parallelism in ZynqNet AI Engine to Accelerate Image Classification in Aerospace

Exploring Parallelism in ZynqNet AI Engine to Accelerate Ima...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Eduardo Marañon Aguilar Fabio Benevenuti Fernanda Lima Kastensmidt Federal University of Rio Grande do Sul (UFRGS) Institute of Informatics Microelectronics Graduate Program (PGMICRO) Porto Alegre Brazil

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

This research investigates various configurations of the Zynqnet AI Engine to accelerate image classification tasks using the SAT-6 dataset and a 4-layer CNN. The C++ code for the hardware accelerator was translated into RTL using Vivado HLS and integrated with the Zynq Processing System on a ZedBoard Zynq-7000 ARM/FPGA SoC. The AI engine was configured to work with 32 -bit floating point, 8bit fixed point and 8 -bit integer type operations, with different processing elements for parallelizing CNN tasks. Given a 64-bit data memory bus in communication with the accelerator and an 8-bit integer quantization, the variation in the number of processing elements does not result in a significant performance improvement. To address this, 8 values were grouped for reading and writing in 64-bit parallel mode, and different communication architectures were designed to improve data transfer between the accelerator and DDR memory, with optional enablement of L1D and L2 cache. The research analyzes CNN computation performance and FPGA resource usage (LUTs, FFs, BRAMs, DSPs) across configurations, providing insights into the trade-offs in FPGA-based CNN implementations, aiding the development of efficient, high-performance hardware accelerators for Deep Learning applications.

关键词： Quantization (signal) Writing Table lookup System-on-chip Convolutional neural networks Artificial intelligence Hardware acceleration Engines Field programmable gate arrays Image classification

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Jitter Due to Random Telegraph Noise in Voltage-Controlled Oscillators Based on Ring Oscillators

Jitter Due to Random Telegraph Noise in Voltage-Controlled O...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Caroline P. Garcia Bernardo Lourosa Gilson I. Wirth Graduate Program in Microelectronics (PGMicro) Universidade Federal do Rio Grande do Sul Porto Alegre Brazil Electrical Engineering Department (DELET) Universida de Federal do Rio Grande do Sul Porto Alegre Brazil

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

As transistors dimensions shrink to nanometer sizes, the variability of their electrical parameters becomes a significant factor in the performance of integrated circuits. Random Telegraph Noise (RTN) is a time-dependent variability that changes the drain current (or threshold voltage) of metal-oxide-semiconductor field-effect transistors (MOSFETs) from one instant in time to the other, leading to jitter in oscillating circuits, such as ring and voltage-controlled (VCO) oscillators. This work evaluates the time-domain jitter caused by the RTN in a capacitive and a current-controlled ring oscillator-based VCO. Different concepts of jitter (absolute jitter, period jitter, and cycle-to-cycle jitter) are studied, focusing on the influence of time window sizes on the jitter amplitude. Monte Carlo simulations are employed for both oscillators, considering a modified SPICE simulator to properly include the RTN impact on the threshold voltage of the transistors.

关键词： Ring oscillators Monte Carlo methods Voltage-controlled oscillators Noise Jitter SPICE Threshold voltage Transistors Autocorrelation Time-domain analysis

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Improved optical enhancement using double-width plasmonic gratings with nanogaps

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Photonics Research 2016年第5期4卷 173-180页

作者： Ahmad A.Darweesh Stephen J.Bauman Joseph B.Herzog Microelectronics-Photonics Graduate Program University of Arkansas Department of Physics University of Arkansas

Plasmonic grating structures have been shown effective at increasing near-field optical enhancement. A doublewidth plasmonic grating design is introduced, where each period has two alternating metal widths separated by a nanogap. With this new design, analysis has shown that plasmonic resonances couple between each metal section,resulting in even greater optical enhancement compared with single-width gratings. The geometry that gives the greatest optical enhancement has been determined with a computational model. This work demonstrates that the increased enhancement is due to hybridized modes that couple between the two grating segments.

关键词： Improved optical enhancement using double-width plasmonic gratings with nanogaps nm

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A 37 nW MOSFET-Only Voltage Reference in 0.13 μm CMOS 33

A 37 nW MOSFET-Only Voltage Reference in 0.13 μm CMOS

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33rd Symposium on Integrated Circuits and Systems Design, SBCCI 2020

作者： de Lima, Vanessa F. Klimach, Hamilton UFRGS Microelectronics Graduate Program Porto Alegre RS Brazil

ISBN: (数字)9781728196251

ISBN: (纸本)9781728196251

This work presents the design of a MOS-only voltage reference with nano-watt power consumption. The proposed circuit consists of a threshold voltage monitor circuit cascaded with a high-slope proportional to absolute temperature (PTAT) voltage generator. The operation of the circuit is analytically described and a design methodology is presented. The proposed circuit was designed and simulated in a standard 130 nm CMOS process while consuming just 37 nW under 1.2 V of power supply at room temperature. Simulation results present a 585 mV reference voltage with a typical temperature coefficient (TC) of 10.13 ppm/°C, for a temperature range from -40 to 125 °C, a power supply rejection ratio (PSRR) of -54.41 dB at 100 Hz, and a line sensitivity of 0.071 %/V was found for a supply range from 1 V to 1.8 V. Monte-Carlo simulations are presented to evaluate the sensitivity to fabrication variability. The estimated silicon area is 0.0078 mm2. © 2020 IEEE.

关键词： Threshold voltage

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A CMOS low noise transconductance amplifier for 1-6 GHz bands 6

A CMOS low noise transconductance amplifier for 1-6 GHz band...

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6th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2015

作者： Cordova, David Fabris, Eric Bampi, Sergio NSCAD Microelectronics Porto Alegre RS Brazil Graduate Program on Microelectronics UFRGS Porto Alegre Brazil

ISBN: (纸本)9781479983322

The linearity and noise requirements in multi-band multi-standard applications make the design of RF CMOS circuits very challenging. A wideband low-noise transconductance amplifier (LNTA) in CMOS 0.13 μm technology that operates between 1-6 GHz is presented. The LNTA is based on a shunt-feedback (SFB) amplifier with current-reuse scheme and employing the noise-canceling technique used in low-noise amplifier designs for wideband input matching. Simulation results show a good trade-off between noise and power-consumption across the frequency span with an average noise figure of 4 dB and a minimum transconductance of 42 mS over the entire band. Performance variations were estimated at 2 GHz with Monte Carlo analysis. The total power consumption is 8.4 mW from 1.2 V supply. © 2015 IEEE.

关键词： Low noise amplifiers

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Attribution of Fano resonant features to plasmonic particle size, lattice constant, and dielectric wavenumber in square nanoparticle lattices

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Photonics Research 2014年第1期2卷 15-23页

作者： Drew DeJarnette Justin Norman D.Keith Roper Microelectronics and Photonics Graduate Program University of ArkansasFayettevilleArkansas 72701USA Department of Chemical Engineering University of ArkansasFayettevilleArkansas 72701USA

Fano resonances between plasmons and diffracted light offer tunable energies and locales,but attribution of Fano resonance features to geometry and physicochemistry of metal nanostructures and adjacent dielectrics has been confounded by complexity and computational *** work shows predictable modal shifts of Fano resonance in square lattices of plasmonic nanostructures can be attributed directly to changes in medium wavenumber,particle size,and lattice constant that alter plasmon polarizability and diffractive *** 45 to 80 nm radius particles,a window of lattice constants that support Fano resonances is identified in a range from 500 to 900 *** constants that support high intensity resonances are determined by individual particle polarizability and medium *** resonance wavelengths redshift from diffracted photon energies as local refractive index(RI)changes due to coupling with particle polarizability in the *** sensitivities for quadrupole,dipole,and Fano resonances are 150,348,and 541 nm,respectively,per RI *** resonance intensity may be enhanced more than tenfold by selecting nanoparticle sizes and lattice *** quantitative effects of such parametric changes are rapidly and intuitively distinguished using a semi-analytic approach,consisting of an exact expression for particle polarizability,a trigonometric description of diffraction,and a semianalytical coupled dipole approximation.

关键词： lattice particle wave

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An Optimized VLSI Exponential Unit Design Exploring Efficient Arithmetic Operation Strategies 30

An Optimized VLSI Exponential Unit Design Exploring Efficien...

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30th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2023

作者： Da Costa, Patrícia Da Rosa, Morgana Soares, Rafael Da Costa, Eduardo Bampi, Sergio Federal University of Rio Grande Do Sul Graduate Program on Microelectronics Porto Alegre Brazil Graduate Program on Computing Pelotas Brazil Graduate Program on Electronic Engineering and Computing Pelotas Brazil Porto Alegre Brazil

ISBN: (纸本)9798350326499

This work presents an optimized exponential function VLSI hardware design by Taylor series expansion. The proposed architecture implements the exponential by approximating the logic design of a 4th-order Taylor series and explores efficient CMOS arithmetic operation strategies. It implements a shift-based divider and explores an efficient 4-2 adder compressor in the adder tree. The proposal with a -7 to 11 input values range shows an output error of around 2% of MRED with a reduced energy consumption of 3.63 pJ/operation for 32-bit output. For a 64-bit output, the energy per operation of the VLSI exponential unit is 14.97pJ/op, being able to process a more comprehensive input range (i.e., -14 to 22) for a negligible mean output error of around 1.7% of MRED. © 2023 IEEE.

关键词： Adders

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