检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

128 篇 会议
28 篇 期刊文献

馆藏范围

156 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

65 篇 工学
- 41 篇 电子科学与技术（可...
- 20 篇 电气工程
- 19 篇 计算机科学与技术...
- 12 篇 材料科学与工程（可...
- 12 篇 软件工程
- 9 篇 化学工程与技术
- 8 篇 动力工程及工程热...
- 6 篇 冶金工程
- 5 篇 机械工程
- 5 篇 仪器科学与技术
- 5 篇 信息与通信工程
- 4 篇 光学工程
- 4 篇 生物医学工程（可授...
- 2 篇 纺织科学与工程
- 2 篇 生物工程
38 篇 理学
- 30 篇 物理学
- 12 篇 数学
- 8 篇 化学
- 6 篇 统计学（可授理学、...
- 3 篇 生物学
- 1 篇 海洋科学
- 1 篇 地球物理学
5 篇 管理学
- 5 篇 管理科学与工程(可...
- 3 篇 工商管理
3 篇 法学
- 3 篇 社会学
3 篇 医学
- 3 篇 临床医学
- 2 篇 基础医学(可授医学...
1 篇 经济学
- 1 篇 应用经济学
1 篇 教育学
- 1 篇 教育学

主题

18 篇 computer archite...
18 篇 hardware
13 篇 threshold voltag...
13 篇 transistors
13 篇 logic gates
12 篇 adders
11 篇 mosfet
9 篇 semiconductor de...
9 篇 power dissipatio...
8 篇 integrated circu...
7 篇 cmos integrated ...
7 篇 standards
7 篇 energy efficienc...
6 篇 tools
6 篇 video coding
6 篇 very large scale...
6 篇 topology
6 篇 capacitors
5 篇 power demand
5 篇 energy consumpti...

机构

13 篇 graduate program...
12 篇 graduate program...
10 篇 microelectronics...
8 篇 graduate program...
7 篇 graduate program...
5 篇 graduate program...
5 篇 ceitec s.a. semi...
4 篇 electrical engin...
4 篇 graduate program...
4 篇 department of el...
4 篇 microelectronics...
4 篇 graduate program...
4 篇 informatics inst...
3 篇 graduate program...
3 篇 microelectronics...
3 篇 senai institute ...
3 篇 electrical engin...
3 篇 graduate program...
3 篇 microelectronics...
3 篇 graduate program...

作者

62 篇 sergio bampi
20 篇 guilherme paim
18 篇 hamilton klimach
17 篇 bampi sergio
10 篇 eric fabris
9 篇 david cordova
9 篇 eduardo costa
8 篇 pedro toledo
7 篇 klimach hamilton
7 篇 tiago r. balen
7 篇 eduardo a. c. da...
7 篇 eduardo da costa
6 篇 pedro t. l. pere...
6 篇 mateus grellert
5 篇 leandro m. g. ro...
5 篇 brito juan pablo...
5 篇 leonardo bandeir...
4 篇 luciano agostini
4 篇 marcelo porto
4 篇 morgana m. a. da...

语言

153 篇 英文
3 篇 中文

检索条件"机构=Graduate Program in Microelectronics"

共 156 条记录，以下是91-100 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Numerical analysis of the harmonics influence on linear interpolation for Power Quality assessment

Numerical analysis of the harmonics influence on linear inte...

引用

International Conference on Harmonics and Quality of Power

作者： Cesar David Paredes Crovato Leonardo Bandeira Soares Sergio Bampi Electrical Engineering Graduate Program-PPGEE Feevale University Unisinos University Novo Hamburgo/Sao Lepoldo Brazil Microelectronics Graduate Program-PGMicro-Informatics Federal University of Rio Grande do Sul-UFRGS Porto Alegre Brazil

This paper presents a numerical analysis to determine the minimum sampling frequency for which a linear interpolation of AC Power signals can be reliably used in the digital domain, regarding the harmonics influence for Power Quality (PQ) assessment. The proposed approach of this paper is based on exhaustive simulations which take into account a large combination of distinct values for module and phase of the third and fifth harmonic components at a given range of sampling frequencies. Our results show that the linear interpolation produces spectrum module errors up to 33.38% for a sampling frequency of 250/32 kHz, while the module percentage error is up to 2.08% at 250/4 kHz. The main contribution of this work is to best determine the minimum sampling frequency that can be used, considering the presence of harmonics components, which makes the linear interpolation an efficient technique for PQ assessment. A minimum sampling frequency turns out to be advantageous for the digital signal processing performance and cost.

关键词： Harmonic analysis Interpolation IEC standards Power system harmonics Power quality Electromagnetic compatibility

来源：评论

学校读者我要写书评

暂无评论

Architectural Exploration for Energy-Efficient LMS and NLMS Adaptive Filters VLSI Design

Architectural Exploration for Energy-Efficient LMS and NLMS ...

引用

Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)

作者： Pedro T. L. Pereira Guilherme Paim Eduardo Costa Paulo Flores Sergio Bampi Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Brazil INESC-ID Instituto Superior Técnico ULisboa Portugal

Adaptive filtering plays an essential role in digital signal processing (DSP), being present in many application fields such as noise reduction, telecommunication, and audio signal processing. Notably, the least mean square (LMS) and its normalized version (NLMS) are the most used algorithms due to their simplicity and robustness, which turn them attractive to hardware solutions. This work proposes architectural solutions for LMS and NLMS algorithms targeting an energy-efficient VLSI design. We explore fully sequential, fully parallel, and semi-parallel architectures reusing the hardware as much as possible for both algorithms. It allows for investigating the number of steps necessary for each architecture, demonstrating the energy per operation, circuit area, and throughput savings. The synthesis results highlight the semi-parallel architectures LMS-2 steps and NLMS-3 steps have the best trade-off energy-speed. In addition, we proved the architecture’s energy efficiency in a harmonic canceling case study, achieving more than 60% in energy savings using both filters.

关键词：

来源：评论

学校读者我要写书评

暂无评论

AxASRE: A Novel Approach to Approximate Adder Synthesis Results Estimation.

AxASRE: A Novel Approach to Approximate Adder Synthesis Resu...

引用

International Conference on Dependable Systems and Networks Workshops (DSN-W)

作者： Pedro T. L. Pereira Guilherme Paim Paulo Flores Eduardo Costa Sergio Bampi Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Brazil INESC-ID Instituto Superior Técnico ULisboa Portugal Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Brazil

Thanks to the high energy efficiency achieved by approximate circuits, the exploration of approximate solutions for a wide of applications is the focus of academic and industrial research. However, defining the most appropriate approximation considering the power consumption and accuracy trade-off can be exhaustive. This paper proposes a novel approach to estimate the synthesis results for approximate adders (AxA) with different bit-width and approximation levels based on a database and simple mathematical operations to reduce the synthesis process complexity during an approximate circuit development. We implement the proposed approach to estimate the synthesis results for the Copy, Error-Tolerant Adder I (ETA-I), Lower-part-or (LOA), and Truncation (Trunc) AxAs. Comparing our estimation with real synthesis results obtained by an industrial synthesis tool, we prove the approach’s efficiency by presenting an average error on the estimated parameters (area, power and delay) less than 10% in the worst case. In addition, our approach reduces by more than 25 times the number of synthesis runs when estimating the synthesis results for all circuits in the bit width range of 2 to 64 with all possible approximation levels.

关键词：

来源：评论

学校读者我要写书评

暂无评论

0.9 V, 5 nW, 9 ppm/oC resistorless sub-bandgap voltage reference in 0.18μm CMOS

0.9 V, 5 nW, 9 ppm/oC resistorless sub-bandgap voltage refer...

引用

2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014

作者： Mattia, Oscar E. Klimach, Hamilton Bampi, Sergio Microelectronics Graduate Program Federal University of Rio Grande Do sul Porto Alegre RS Brazil Electrical Engineering Department Federal University of Rio Grande Do sul Porto Alegre RS Brazil Informatics Institute Federal University of Rio Grande Do sul Porto Alegre RS Brazil

ISBN: (纸本)9781479925070

In this work a novel resistorless sub-bandgap voltage reference (BGR) is introduced. It is a self-biased and small area topology that works in the nano-ampere current consumption range, and under 1 V of power supply. The analytical behavior of the circuit is described, and simulation results for a standard 0.18 μm CMOS process are analysed. A reference voltage of 479 mV is demonstrated, with a temperature coefficient of 8.79 ppm/oC for the 0 to 125 °C range, while the power consumption of the whole circuit is 4.86 nW under a 0.9 V power supply at 27 oC. The estimated silicon area is 0.0012 mm2. © 2014 IEEE.

关键词： CMOS integrated circuits

来源：评论

学校读者我要写书评

暂无评论

MOS-only M-2M DAC for ultra-low voltage applications 6

MOS-only M-2M DAC for ultra-low voltage applications

引用

6th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2015

作者： Sperotto, Israel Klimach, Hamilton Bampi, Sergio Microelectronics Graduate Program Federal University of Rio Grande Do sul Porto Alegre RS Brazil Electrical Engineering Department Federal University of Rio Grande Do sul Porto Alegre RS Brazil Informatics Institute Federal University of Rio Grande Do sul Porto Alegre RS Brazil

ISBN: (纸本)9781479983322

This work presents a study of the CMOS based R-2R ladder network (also called M-2M) Digital-to-Analog Converter (DAC) as a potential candidate for ultra-low voltage (ULV) applications, i.e. supply voltages VDD lower than 200mV. MOS transistors operate in subthreshold under such very low VDD, and the circuit analysis must be done using an all-region continuous MOSFET model. Simulation results in a commercial 130 nm process corroborate the presented analysis, showing that it is possible to implement this DAC topology for 6 to 8 bits operating under supply voltages from 70 mV to 140 mV. © 2015 IEEE.

关键词： Digital to analog conversion

来源：评论

学校读者我要写书评

暂无评论

Surface Characterization of Sodium Cholate Treated CVD Graphene

Surface Characterization of Sodium Cholate Treated CVD Graph...

引用

IEEE Conference on Nanotechnology

作者： Evans Addo-Mensah Janet Obaemo Katie Welch Yang Tian Shiva Dolatabadi Hugh Churchill Uchechukwu Wejinya Materials Science and Engineering Graduate Program University of Arkansas Microelectronics and Photonics Program University of Arkansas Department of Physics University of Arkansas Fayetteville Arkansas Department of Mechanical Engineering University of Arkansas Fayetteville Arkansas

The advancement of graphene has created a need in exploring its properties for different applications. One way to explore its properties is by reducing its hydrophobicity. To overcome hydrophobicity of graphene, surfactants have been used in functionalization, hence improving the surface properties of the graphene monolayer. Therefore, investigating surfactant treatment for CVD graphene becomes useful in understanding the surface property effects on graphene. This study utilizes CVD graphene on silicon substrates. Its treatment was done with varying concentrations of Sodium Cholate (SC) for different treatment times. These samples were then characterized using Atomic Force Microscopy (AFM) to investigate the surface properties of the samples before and after treatment. To be optimized, the graphene must remain attached to the silicon substrate. The result shows that the integrity of the graphene, which is basically the Sp2 structure, is preserved as there was no delamination from the substrate even after treatment for as long as 2 hours in 1% weight/volume concentration of the SC solution.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Exploiting approximate adder circuits for power-efficient Gaussian and Gradient filters for Canny edge detector algorithm

Exploiting approximate adder circuits for power-efficient Ga...

引用

IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Julio de Oliveira Leonardo Soares Eduardo Costa Sergio Bampi Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil Graduare Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

This paper proposes the exploration of approximate adders for the implementation of power-efficient Gaussian and Gradient filters for Image Processing. The Gaussian filter is a convolution operator which is used to blur images and to remove noise. On the other hand, the Gradient of an image measures how it is changing. Both blocks can be designed in hardware using only shifts and additions. In this work we exploit a set of approximate adders in order to implement energy-efficient filters. The tree of adders of Gaussian and Gradient filters are implemented using one RCA-based approximate adder, as well as an Error-Tolerant Adder ETAI. The approximate architectures are compared to the best precise implementation of the filters. As the Gaussian and Gradient blocks are part of the Canny edge detector algorithm, we have implemented the adder trees of the filters aiming this application. Our main results show that for an efficient power realization of this algorithm, the best strategy consists in the implementation of the Gaussian filter with ETA I adder, and the Gradient filter with the RCA-based adder.

关键词： Adders Filtering algorithms Image edge detection Computer architecture Detectors Kernel

来源：评论

学校读者我要写书评

暂无评论

Within-die and die-to-die variability on 65nm CMOS : oscillators experimental results

Within-die and die-to-die variability on 65nm CMOS : oscilla...

引用

European Workshop on CMOS Variability (VARI)

作者： Juan Pablo Martinez Brito Marcelo Lubaszewski Sergio Bampi CEITEC S.A. Semiconductors Porto Alegre Brazil Graduate Program on Microelectronics - PGMICRO - Informatics Institute Federal University of Rio Grande do Sul- UFRGS

This paper presents experimental data and analyses from the oscillation frequency of CMOS ring oscillators (ROs). The measurements are analyzed in order to separate the coefficient of variation (CV = σ/μ) behavior of both within-die (WID) process variations and Die-to-Die (D2D) process variations. Three different RO's sizes distributed over a total of 96 ROs per chip were measured in 32 different chip samples, all from a single MOSIS Multi-Project-wafer in a commercial 65nm CMOS process. All ROs were measured with varying power supply voltages, from nominal VDD (1.2V) down to nearthreshold (0.45V), resulting in a sample space of 18.432 points of interest. Statistical analysis results are shown regarding each RO stage size, the applied power supply and the correlation of both to the WID and D2D variations. The increase on D2D and WID coefficients of variations at the near-threshold supplies is very significant, as explained by increased delay variability at the moderate inversion regime of the FETs. The 96 test ROs occupy a total area of 200 x 480 μm 2 in each test chip.

关键词： Frequency measurement Ring oscillators Semiconductor device measurement Inverters Transistors CMOS integrated circuits Standards

来源：评论

学校读者我要写书评

暂无评论

A Configurable Pruning Gaussian Image Filter for Energy-Efficient Edge Detection

A Configurable Pruning Gaussian Image Filter for Energy-Effi...

引用

IEEE International Conference on Electronics, Circuits and Systems

作者： Leonardo Bandeira Soares Eduardo Antonio Cesar da Costa Sergio Bampi Federal Institute of Technology of Rio Grande do Sul (IFRS) Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil Graduate Program on Microelectronics Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

This paper presents a new configurable pruning Gaussian image filter CMOS architecture to address energy efficiency requirements regarding edge detection applications. Low-energy consumption is key for Internet of Things (IoT) devices. Many emerging IoT applications rely on cameras to extract video or image features by running power-hungry computer vision algorithms. The Gaussian image filter is one of the most compute intensive tasks for pre-processing edge detection techniques which are widely adopted in the computer vision domain. Therefore, our proposed 2D Gaussian filter architecture enables: i) a low power and low area overhead runtime configuration scheme based on clock gating technique to prune the Gaussian filter (GF) window size, and ii) run-time capability to balance the tradeoff between edge detection quality and energy efficiency. Our proposed configurable architecture is synthesized and mapped onto 45 nm technology for an ASIC implementation. Results show that for 6 different run-time profiles our proposed configurable architecture provides power dissipation reduction of up to 64% with multiple levels of edge detection quality, which is assessed by considering the performance conformance metric.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Memory energy consumption analyzer for video encoder hardware architectures

Memory energy consumption analyzer for video encoder hardwar...

引用

IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Livia Amaral Guilherme Povala Marcelo Porto Dieison Silveira Sergio Bampi Federal University of Pelotas Brazil Group of Architectures and Integrated Circuits (GACI) Federal University of Rio Grande do Sul Brazil Graduate Program in Microelectronics (PGMicro)

ISBN: (纸本)9781509061143

The motion estimation stage requires high number of memory accesses, causing high-energy consumption in the video coding process. This results in lower battery lifetime on mobile devices. Thus, solutions to reduce the external memory bandwidth in video coding systems must be used. This work proposes a memory energy consumption analyzer, which estimates the energy consumption related to memory accesses of video encoder systems. This analyzer enables the evaluation of different schemes with data reuse, reference frame compression and memory hierarchy, which are the most used techniques for memory bandwidth reduction and its associated energy consumption. This analyzer is implemented in SystemC, which allows system modeling in a simple and fast way. As a case study of the tool, the developed analyzer was used to evaluate a solution joining a reference frame compressor and a Level C data reuse scheme. The energy consumption results of the evaluated scheme present reduction on both write and read memory operations, reaching a total memory energy consumption reduction of 97.91% when compared to original video encoder without any technique for memory access reduction.

关键词： Energy consumption Memory management Video coding Standards Hardware Random access memory Writing

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共16页 << < 6 7 8 9 10 11 12 13 14 15 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：