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European Workshop on CMOS Variability (VARI)

作者： Juan Pablo Martinez Brito Marcelo Lubaszewski Sergio Bampi CEITEC S.A. Semiconductors Porto Alegre Brazil Graduate Program on Microelectronics - PGMICRO - Informatics Institute Federal University of Rio Grande do Sul- UFRGS

This paper presents experimental data and analyses from the oscillation frequency of CMOS ring oscillators (ROs). The measurements are analyzed in order to separate the coefficient of variation (CV = σ/μ) behavior of both within-die (WID) process variations and Die-to-Die (D2D) process variations. Three different RO's sizes distributed over a total of 96 ROs per chip were measured in 32 different chip samples, all from a single MOSIS Multi-Project-wafer in a commercial 65nm CMOS process. All ROs were measured with varying power supply voltages, from nominal VDD (1.2V) down to nearthreshold (0.45V), resulting in a sample space of 18.432 points of interest. Statistical analysis results are shown regarding each RO stage size, the applied power supply and the correlation of both to the WID and D2D variations. The increase on D2D and WID coefficients of variations at the near-threshold supplies is very significant, as explained by increased delay variability at the moderate inversion regime of the FETs. The 96 test ROs occupy a total area of 200 x 480 μm 2 in each test chip.

关键词： Frequency measurement Ring oscillators Semiconductor device measurement Inverters Transistors CMOS integrated circuits Standards

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Near-threshold computing for very wide frequency scaling: Approximate adders to rescue performance

Near-threshold computing for very wide frequency scaling: Ap...

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Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)

作者： L. B. Soares Sergio Bampi A. L. R. Rosa E. A. C. Costa Graduate Program on Microelectronics (PGMicro) PPGC - Informatics Institute Federal University of Rio Grande do Sul (UFRGS) Catholic University of Pelotas (UCPEL) Porto Alegre Brazil

Near-threshold computing in CMOS is a promising alternative for any application which can tolerate very wide voltage-frequency scaling (VFS). Internet-of-Things (IoT) devices will operate in very different power-performance modes, from sub-MHz to peaks of hundreds of MHz. The nano-power range which is achievable in deca-nanometer CMOS at near-VT is the alternative we explore for VLSI circuits (8051 processor, filters, and ISCAS benchmark circuits). This paper proposes a method to design CMOS circuits for a wide dynamic range of VFS, and targets near-threshold for best efficiency. A standard-cell based design methodology specific for near-VT is demonstrated here in for a commercial 65nm CMOS process. Power and timing variability are characterized, so that variation-aware and yet ultra-low supply voltage designs are enabled. Our cell design method avoids unnecessary upsizing and it focus on near- and well above threshold regions of operation. For the study cases of medium complexity notch filter design (24kgates), and an 8051 compatible core (20kgates) we demonstrate 63X to 77X energy/operation savings for applications that tolerate ultra-wide frequency scaling (from hundreds of KHz to 1GHz) in their operating modes. The results were obtained using the minimal cycle time achievable at each supply voltage. The extremely low and highly-variable performance at sub- and near-VT have to be addressed by new logic design paradigms. In this paper we also exploit the use of approximate adders to increase the timing performance of a class of digital filter circuits, to enable compensating the performance loss inherent to near-VT operation in CMOS. Our results show that the effort to explore energy savings in low power optimized circuits through the approximate computing approach is validated with energy and worst path delay reductions up to 19.4% and 36.7% respectively, compared to the precise arithmetic implementation, without compromising the filters frequency response. Our a

关键词： Finite impulse response filters Adders CMOS integrated circuits Libraries Approximation methods Energy efficiency Timing

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Attribution of Fano resonant features to plasmonic particle size, lattice constant, and dielectric wavenumber in square nanoparticle lattices

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Photonics Research 2014年第1期2卷 15-23页

作者： Drew DeJarnette Justin Norman D.Keith Roper Microelectronics and Photonics Graduate Program University of ArkansasFayettevilleArkansas 72701USA Department of Chemical Engineering University of ArkansasFayettevilleArkansas 72701USA

Fano resonances between plasmons and diffracted light offer tunable energies and locales,but attribution of Fano resonance features to geometry and physicochemistry of metal nanostructures and adjacent dielectrics has been confounded by complexity and computational *** work shows predictable modal shifts of Fano resonance in square lattices of plasmonic nanostructures can be attributed directly to changes in medium wavenumber,particle size,and lattice constant that alter plasmon polarizability and diffractive *** 45 to 80 nm radius particles,a window of lattice constants that support Fano resonances is identified in a range from 500 to 900 *** constants that support high intensity resonances are determined by individual particle polarizability and medium *** resonance wavelengths redshift from diffracted photon energies as local refractive index(RI)changes due to coupling with particle polarizability in the *** sensitivities for quadrupole,dipole,and Fano resonances are 150,348,and 541 nm,respectively,per RI *** resonance intensity may be enhanced more than tenfold by selecting nanoparticle sizes and lattice *** quantitative effects of such parametric changes are rapidly and intuitively distinguished using a semi-analytic approach,consisting of an exact expression for particle polarizability,a trigonometric description of diffraction,and a semianalytical coupled dipole approximation.

关键词： lattice particle wave

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Approximate adder synthesis for area- and energy-efficient FIR filters in CMOS VLSI

Approximate adder synthesis for area- and energy-efficient F...

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Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)

作者： Leonardo Bandeira Soares Sergio Bampi Eduardo Costa Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil Polytechnique Institute Catholic University of Pelotas (UCPEL) Pelotas Brazil

This paper proposes the synthesis of approximate adders to improve the area and energy efficiency of FIR filters implemented in CMOS. We demonstrate energy per sample savings and hardware area reduction in the filters with our design method. All savings are in addition to the improvements obtained on previously optimized digital filters in which state-of-the-art multiplierless multiple constant multiplication optimizations are included in the design method. Digital finite impulse response filters are largely used in multimedia systems which can tolerate levels of approximations in computing or loss of accuracy in the arithmetic dataflow. Our work deals with different levels of approximation in ripple-carry adders which are part of the filters implemented in hardware, fully synthesized in CMOS, and later compared to the best precise implementation of the same filter. Our results show that the effort to explore area and energy savings in low power optimized circuits through the approximate computing approach is validated with area and energy reductions up to 18.8% and 15.5% respectively, without compromising the filters frequency response or the Signal to Noise Ratio (SNR) of recorded 16-bit audio signals. Our approximate adder method enables a higher degree of area and energy efficiencies in CMOS VLSI filters.

关键词： Finite impulse response filters Adders Approximation methods Signal to noise ratio CMOS integrated circuits Energy efficiency

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Design and Linearity Analysis of a M-2M DAC for Very Low Supply Voltage

Design and Linearity Analysis of a M-2M DAC for Very Low Sup...

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IEEE International Conference on Electronics, Circuits, and Systems

作者： Israel Sperotto Hamilton Klimach Sergio Bampi Microelectronics Graduate Program Federal University of Rio Grande do Sul Electrical Engineering Department Federal University of Rio Grande do Sul Informatics Institute Federal University of Rio Grande do Sul

ISBN: (纸本)9781509002474

This work presents the design of a 6 bits M-2M ladder Digital-to-Analog Converter (DAC) proper for operation under supply voltages of 200 mV or lower. Since the MOS transistors are operating in the subthreshold region under such low supply, the mismatch analysis was done using an all-region continuous MOSFET model. The performance of the circuit is evaluated through simulations and the trade-offs between linearity, supply voltage and sampling rate are investigated in the paper. It is proposed that a 6 bits M-2M DAC operating under 200 mV and with sampling rate of 5.1MS/s is feasible using a commercial 130 nm process and standard transistors.

关键词： supply voltage metal-oxide-semiconductor field effect transistors DERIVED AIR CONCENTRATION Development Assistance Committee sampling rate Linearity Drill bits

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Direct growth of Ge_1-xSn_x films on Si using a cold-wall ultra-high vacuum chemical-vapor-deposition system

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FRONTIERS IN MATERIALS 2015年 2卷

作者： Mosleh, Aboozar Alher, Murtadha A. Cousar, Larry C. Du, Wei Ghetmiri, Seyed Amir Pham, Thach Grant, Joshua M. Sun, Greg Soref, Richard A. Li, Baohua Naseem, Hameed A. Yu, Shui-Qing Microelectronics-Photonics Graduate Program (μEP) University of Arkansas Fayetteville AR USA Department of Electrical Engineering University of Arkansas Fayetteville AR USA Mechanical Engineering Department University of Karbala Karbala Iraq Arktonics LLC Fayetteville AR USA Engineering-Physics Department Southern Arkansas University Magnolia AR USA Department of Engineering University of Massachusetts Boston Boston MA USA

Germanium tin alloys were grown directly on Si substrate at low temperatures using a cold wall ultra-high vacuum chemical-vapor-deposition system. Epitaxial growth was achieved by adopting commercial gas precursors of germane and stannic chloride without any carrier gases. The X-ray diffraction analysis showed the incorporation of Sn and that the Gei,Sn, films are fully epitaxial and strain relaxed. Tin incorporation in the Ge matrix was found to vary from 1 to 7%. The scanning electron microscopy images and energy-dispersive X-ray spectra maps show uniform Sn incorporation and continuous film growth. Investigation of deposition parameters shows that at high flow rates of stannic chloride the films were etched due to the production of HCI. The photoluminescence study shows the reduction of band-gap from 0.8 to 0.55 eV as a result of Sn incorporation.

关键词： chemical-vapor-deposition Si photonics Ge alloys photoluminescence Ge-Sn

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Electromechanical Properties of One Dimensinal Carbon Chains

Electromechanical Properties of One Dimensinal Carbon Chains

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IEEE International Conference on Nano/Molecular Medicine and Engineering

作者： Zeina Salman Arun Nair Steve Tung Microelectronics and Photonics Graduate Program University of Arkansas Fayetteville Arkansas 72701 USA Department of Mechanical Engineering University of Arkansas Fayetteville Arkansas 72701 USA

ISBN: (纸本)9781467396738

Carbon based nanostructures such as graphene and carbon nanotubes have received widespread attention due to their unique mechanical and electronic properties. This paper describes a quantum mechanics based study of the electronic band structures and transport properties of one-dimensional (1D) carbon chains, the thinnest nanowires available in nature. The study is based on the application of density functional theory and non-equilibrium Green's function where maximally localized Wannier functions and Landauer formalism are combined to compute the electronic band structures and quantum conductance of the 1D carbon chains. The simulation result indicates that the peak quantum conductance of 1D carbon chains is about five times smaller than that of carbon nanotubes. However, the quantum conductance is also a function of the length and chemical bonds of the carbon chains. When the carbon chains are mechanically strained at 3%, the quantum conductance is reduced by about 50%. This result suggests 1D carbon chains can provide ultra high-resolution electromechanical measurements of important biomolecules such as DNA.

关键词： Carbyne Chains First-principle simulation Localized Wannier Functions Quantum Conductance

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MOS-only M-2M DAC for ultra-low voltage applications

MOS-only M-2M DAC for ultra-low voltage applications

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Israel Sperotto Hamilton Klimach Sergio Bampi Microelectronics Graduate Program Federal University of Rio Grande do Sul Porto Alegre RS Brazil Electrical Engineering Department Federal University of Rio Grande do Sul Porto Alegre RS Brazil Informatics Institute Federal University of Rio Grande do Sul Porto Alegre RS Brazil

This work presents a study of the CMOS based R-2R ladder network (also called M-2M) Digital-to-Analog Converter (DAC) as a potential candidate for ultra-low voltage (ULV) applications, i.e. supply voltages VDD lower than 200mV. MOS transistors operate in subthreshold under such very low VDD, and the circuit analysis must be done using an all-region continuous MOSFET model. Simulation results in a commercial 130 nm process corroborate the presented analysis, showing that it is possible to implement this DAC topology for 6 to 8 bits operating under supply voltages from 70 mV to 140 mV.

关键词： MOSFET Semiconductor device modeling Analytical models Mathematical model CMOS integrated circuits Integrated circuit modeling

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Sub-1 v supply nano-watt MOSFET-only threshold voltage extractor circuit 14

Sub-1 v supply nano-watt MOSFET-only threshold voltage extra...

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27th Symposium on Integrated Circuits and Systems Design, SBCCI 2014

作者： Mattia, Oscar E. Klimach, Hamilton Bampi, Sergio Microelectronics Graduate Program Federal University of Rio Grande Do sul Porto Alegre Brazil Electrical Engineering Department Federal University of Rio Grande Do sul Porto Alegre Brazil Informatics Institute Federal University of Rio Grande Do sul Porto Alegre Brazil

ISBN: (纸本)9781479968732

This work presents a self-biased MOSFET threshold voltage VT0 extractor circuit. Its working principle is based on a current-voltage relationship derived from a continuous physical model. The model is valid for any operating condition, from weak to strong inversion, and under triode or saturation regimes. The circuit is MOSFET-only (can be implemented in any standard digital process), and it operates with a power supply of less than 1 V, consuming tenths of nW. Post-layout simulation results show that the extracted VT0 has an error inferior to 1.3%, when compared to the theoretical value, for a -40 to 125°C temperature range. We present variability results from Monte Carlo simulations that support the extracting behavior of the circuit with good accuracy. The occupied silicon area is 0.0076 mm2 in a 0.13μm CMOS process. © 2014 IEEE.

关键词： Threshold voltage

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Numerical analysis of the harmonics influence on linear interpolation for Power Quality assessment

Numerical analysis of the harmonics influence on linear inte...

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International Conference on Harmonics and Quality of Power

作者： Cesar David Paredes Crovato Leonardo Bandeira Soares Sergio Bampi Electrical Engineering Graduate Program-PPGEE Feevale University Unisinos University Novo Hamburgo/Sao Lepoldo Brazil Microelectronics Graduate Program-PGMicro-Informatics Federal University of Rio Grande do Sul-UFRGS Porto Alegre Brazil

This paper presents a numerical analysis to determine the minimum sampling frequency for which a linear interpolation of AC Power signals can be reliably used in the digital domain, regarding the harmonics influence for Power Quality (PQ) assessment. The proposed approach of this paper is based on exhaustive simulations which take into account a large combination of distinct values for module and phase of the third and fifth harmonic components at a given range of sampling frequencies. Our results show that the linear interpolation produces spectrum module errors up to 33.38% for a sampling frequency of 250/32 kHz, while the module percentage error is up to 2.08% at 250/4 kHz. The main contribution of this work is to best determine the minimum sampling frequency that can be used, considering the presence of harmonics components, which makes the linear interpolation an efficient technique for PQ assessment. A minimum sampling frequency turns out to be advantageous for the digital signal processing performance and cost.

关键词： Harmonic analysis Interpolation IEC standards Power system harmonics Power quality Electromagnetic compatibility

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