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IEEE International Conference on Nano/Micro Engineered and Molecular Systems

作者： Abayomi Omolewu Guangyi Shi Tian Ryan Xiangbo Meng Uchechukwu Wejinya Microelectronics-Photonics Graduate Program University of Arkansas Fayetteville Arkansas USA Scics Peking University at Wuxi Wuxi China Chemistry and Biochemistry Department University of Arkansas Fayetteville Arkansas USA Department of Mechanical Engineering University of Arkansas Fayetteville Arkansas USA

Chemical functionalization is a method that is being explored to take advantage of the intriguing properties of graphene and its derivatives. Surfactant treatments have been successfully employed to non-covalently functionalize graphitic materials such as carbon nanotube and graphite. However, there is still need to investigate the surfactant treatment approach for commercially available chemical vapor deposited (CVD) graphene on silicon-silicon dioxide substrate. CVD graphene is one of the large-scale graphene available;hence, it is essential to understand how surfactants interact with it. This work presents the optical and atomic force microscopy study of non-covalently-functionalized graphene using Sodium Dodecyl Sulphate. CVD graphene on silicon/silicon dioxide (Si/SiO_2) substrates were treated with different surfactant concentrations for different times. Unlike other derivatives of graphene, like carbon nanotube and graphite where the delamination of graphene sheet from the substrate is not a major concern, results show that the stability of the CVD graphene on the substrate is highly dependent on the concentration of the surfactant used for modifying the surface of the graphene, and the duration of treatment. Higher concentration of surfactant treatment was achieved by dissolving the surfactant with water and isopropyl alcohol. The result also suggests that different concentrations of surfactant affect the surface roughness of the functionalized graphene.

关键词： Graphene Surfactants Substrates Delamination Nanoparticles Zinc oxide

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Low cost automatic test vector generation for structural analog testing

Low cost automatic test vector generation for structural ana...

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Latin American Test Workshop, LATW

作者： André L. Chinazzo Paulo C. Comassetto de Aguirre Tiago R. Balen Microelectronic System Design Group Technische Universität Kaiserslautern Kaiserslautern Germany Universidade Federal do Pampa Bage RS BR Graduate Program on Microelectronics Universidade Federal do Rio Grande do Sul Porto Alegre RS Brazil

ISBN: (纸本)9781538604168

This work presents a low cost automatic method to test vector generation for defect-oriented structural analog testing. An optimal set of analog single tone signals is obtained by computing the frequency response of circuit nodes, while iteratively injecting faults, using a SPICE simulator. The method also allows to identify the nodes of the circuit with higher observabilities to the injected faults, by comparing the obtained fault coverage as a function of frequency. A 130 nm ΣΔ modulator is used as case study to validate the technique under fault injection campaigns. Up to 100% fault coverage is obtained depending on the number of test points. A trade-off is identified, in such a way that a single test point may be used, achieving 95% of fault coverage. The optimized sets of single tone signals can be either combined in a multi-tone testing strategy or sequentially applied during the test application phase.

关键词： Circuit faults Frequency modulation Integrated circuit modeling Frequency response Transistors

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A 90 dB PSRR, 4 dBm EMI Resistant, NMOS-Only Voltage Reference using Zero-VT Active Loads

A 90 dB PSRR, 4 dBm EMI Resistant, NMOS-Only Voltage Referen...

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IEEE International Symposium on Electromagnetic Compatibility

作者： David Cordova Hamilton Klimach Sergio Bampi Eric Fabris NSCAD Microeletronica - UFRGS - Porto Alegre RS Brazil Graduate Program on Microelectronics - UFRGS - Porto Alegre RS Brazil

ISBN: (纸本)9781509014439

Electromagnetic Interference (EMI) disturbances coupled in the power supply of voltage and current references can severely degrade their performance, due to its finite Power Supply Rejection Ratio (PSRR). The design of a 90 dB PSRR, 4 dBm EMI resistant NMOS-Only Voltage Reference is herein presented. The Voltage Reference is designed based on the Zero Temperature Coefficient (ZTC) transistor point. The high-PSRR is obtained using zero-VT transistors as active loads in the open and feedback loop of the circuit. The final circuit was designed in a 130 nm CMOS process and occupies around 0.014 mm~2 of silicon area while consuming just 1.15 μW. Post-layout simulations present a 206 mV of Voltage Reference with a Temperature Coefficient of 321 ppm/℃, for the temperature range from -55 to 125 ℃. An EMI source of 4 dBm (1 V_(pp)) injected in the power supply, according to the Direct Power Injection (DPI) standard, yield in a maximum dc shift and Peak-to-peak ripple of -0.17 % and 822 μV_(pp), respectively.

关键词： zero-VT Transistor Voltage Reference Electromagnetic Compatibility and Interference ZTC Condition

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Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects

Evaluating the Impact of Ionizing Particles on FinFET -based...

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Latin American Test Workshop, LATW

作者： Thiago Copetti Guilherme Cardoso Medeiros Mottaqiallah Taouil Said Hamdioui Letícia Bolzani Poehls Tiago Balen Graduate Program on Microelectronics - PGMICRO Federal University of Rio Grande do Sul Porto Alegre Brazil Computer Engineering Laboratory Delft University of Technology Delft The Netherlands School of Engineering Pontifical Catholic University of Rio Grande do Sul Porto Alegre Brazil

ISBN: (数字)9781728187310

ISBN: (纸本)9781728187327

Fin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. Despite demonstrating improvements on short channel effect and overcoming the growing leakage problem of planar CMOS technology, the continuity of feature size miniaturization allowed by FinFETs tends to increase sensitivity to Single Event Upsets (SEUs) caused by ionizing particles, especially in blocks with higher transistor densities as Static Random-Access Memories (SRAMs). Variation during the manufacturing process has introduced different types of defects that directly affect the SRAM's reliability, such as weak resistive defects. As some of these defects may cause dynamic faults, which require more than one consecutive operation to sensitize the fault at the logic level, traditional test approaches may fail to detect them and test escapes can occur. These undetected faults associated with weak resistive defects may affect the FinFET -based SRAM reliability during the lifetime. In this context, this paper proposes to investigate the impact of ionizing particles on the reliability of FinFET -based SRAMs in the presence of weak resistive defects. Firstly, a TCAD model of a FinFET-based SRAM cell is proposed in order to allow the evaluation of the ionizing particle's impact. Then, SPICE simulations are performed considering the current pulse parameters obtained with TCAD. In this step, weak resistive defects are injected into the FinFET-based SRAM cell. Results show that weak defects may have either a positive or negative influence on the cell reliability against SEUs caused by ionizing particles.

关键词： FinFETs SRAM cells Computational modeling Reliability SPICE Transient analysis

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Direct growth of Ge_1-xSn_x films on Si using a cold-wall ultra-high vacuum chemical-vapor-deposition system

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FRONTIERS IN MATERIALS 2015年 2卷

作者： Mosleh, Aboozar Alher, Murtadha A. Cousar, Larry C. Du, Wei Ghetmiri, Seyed Amir Pham, Thach Grant, Joshua M. Sun, Greg Soref, Richard A. Li, Baohua Naseem, Hameed A. Yu, Shui-Qing Microelectronics-Photonics Graduate Program (μEP) University of Arkansas Fayetteville AR USA Department of Electrical Engineering University of Arkansas Fayetteville AR USA Mechanical Engineering Department University of Karbala Karbala Iraq Arktonics LLC Fayetteville AR USA Engineering-Physics Department Southern Arkansas University Magnolia AR USA Department of Engineering University of Massachusetts Boston Boston MA USA

Germanium tin alloys were grown directly on Si substrate at low temperatures using a cold wall ultra-high vacuum chemical-vapor-deposition system. Epitaxial growth was achieved by adopting commercial gas precursors of germane and stannic chloride without any carrier gases. The X-ray diffraction analysis showed the incorporation of Sn and that the Gei,Sn, films are fully epitaxial and strain relaxed. Tin incorporation in the Ge matrix was found to vary from 1 to 7%. The scanning electron microscopy images and energy-dispersive X-ray spectra maps show uniform Sn incorporation and continuous film growth. Investigation of deposition parameters shows that at high flow rates of stannic chloride the films were etched due to the production of HCI. The photoluminescence study shows the reduction of band-gap from 0.8 to 0.55 eV as a result of Sn incorporation.

关键词： chemical-vapor-deposition Si photonics Ge alloys photoluminescence Ge-Sn

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The Impact of Hot Carrier Injection-Induced Device Degradation for Lower-Power FinFETs

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Journal of Electronic Materials 2023年第2期52卷 1391-1399页

作者： Chen, Yu-Lin Yeh, Wen-Kuan Hsu, Heng-Tung Chen, Ke-Horng Lien, Der-Hsien Lin, Wen-Chin Yu, Tien-Han Chiu, Yu-Sheng Godwinraj, D. Godfrey, D. Wu, Chien-Hung International College of Semiconductor Technology National Yang Ming Chiao Tung University Hsinchu Taiwan Graduate Degree Program of College of Electrical and Computer Engineering National Yang Ming Chiao Tung University Hsinchu Taiwan Institute of Electronics National Yang Ming Chiao Tung University Hsinchu Taiwan Institute of Microelectronics National Cheng Kung University Tainan Taiwan Department of ECE Amal Jyothi College of Engineering Kerala Kottayam India Department of Optoelectronics and Materials Engineering Chung Hua University Hsinchu Taiwan Department of Electronics and Communication Engineering Dayananda Sagar University Bengaluru India National Applied Research Laboratories Hsinchu Taiwan

The impact of hot carrier injection (HCI) on the performance of standard and low-VT FinFETs are investigated and benchmarked with each other. For this investigation, these FinFETs were fabricated with various gate lengths (L) from 16 to 36 nm. HCI-induced transconductance degradation in standard devices for gate length variations of 36 nm down to 16 nm was 75%, while it was 35% for low-VT devices. Similarly, the degradation of threshold voltage in standard devices for gate length variations of 36 nm down to 16 nm was 39%, while it was 36% for low-VT device. In this work, as the device is subject to HCI, we found that: (1) short-channel devices cause severe degradation on the threshold voltage and transconductance (gm) compared to long-channel devices, owing to the higher electric field for short-channel devices at the gate edge, (2) standard devices exhibit a more stable threshold voltage than that of low-VT power devices, since the TiN barrier layer prevents Al atom diffusion into the HfO2 layer, and (3) the transconductance efficiency of standard devices is better than that of low-VT power devices. Further, the lower-VT devices show lower transconductance degradation than standard devices. However, the transconductance degradation of the long-channel standard and low-VT devices are the same. Compared to short-channel low-VT devices, extended-channel standard devices are more immune to the HCI effect. © 2022, The Minerals, Metals & Materials Society.

关键词： Threshold voltage

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Thermodynamic and Thermoelectric properties of CoFeYGe (Y= Ti, Cr) quaternary Heusler alloys: First principle calculations

arXiv

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arXiv 2019年

作者： Haleoot, Raad Hamad, Bothina Microelectronics and Photonics graduate program University of Arkansas FayettevilleAR72701 United States Department of Physics College of Education University of Mustansiriyah Baghdad10052 Iraq Department of Physics University of Arkansas FayettevilleAR72701 United States Physics Department University of Jordan Amman11942 Jordan

Utilizing a material in thermoelectric applications requires a mechanical, thermal, and lattice stability as well a high figure of merit (ZT). In this work, we present the structural, electronic, magnetic, mechanical, thermodynamic, dynamic, and thermoelectric properties of CoFeYGe (Y = Ti, Cr) quaternary Heusler compounds using the density functional theory (DFT). The calculated mechanical properties and phonon dispersions reveal that the structures of these compounds are stable. Both CoFeCrGe and CoFeTiGe compounds show a ferromagnetic and ferrimagnetic half-metallic behavior with band gaps of 0.41 and 0.38 eV, respectively. The lattice thermal conductivity (κL) exhibits low values that reach 3.01 W/(m.K) (3.47 W/(m.K)) for CoFeCrGe (CoFeTiGe) at 1100 K. The optical phonon modes have a large contribution of 60.2% (70.9 %) to κL value for CoFeCrGe (CoFeTiGe). High ZT values of 0.71 and 0.65 were obtained for CoFeCrGe and CoFeTiGe, respectively. Based on our calculations, CoFeCrGe and CoFeTiGe combine both good spintronic and thermoelectric behaviors that may be used in spin injection applications. Copyright © 2019, The Authors. All rights reserved.

关键词： Density functional theory

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0.9 V, 5 nW, 9 ppm/oC resistorless sub-bandgap voltage reference in 0.18μm CMOS

0.9 V, 5 nW, 9 ppm/oC resistorless sub-bandgap voltage refer...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Oscar E. Mattia Hamilton Klimach Sergio Bampi Microelectronics Graduate Program Federal University of Rio Grande do Porto Alegre RS Brazil Electrical Engineering Department Sul Federal University of Rio Grande do Porto Alegre RS Brazil Informatics Institute Federal University of Rio Grande do Porto Alegre RS Brazil

In this work a novel resistorless sub-bandgap voltage reference (BGR) is introduced. It is a self-biased and small area topology that works in the nano-ampere current consumption range, and under 1 V of power supply. The analytical behavior of the circuit is described, and simulation results for a standard 0.18 μm CMOS process are analysed. A reference voltage of 479 mV is demonstrated, with a temperature coefficient of 8.79 ppm/°C for the 0 to 125°C range, while the power consumption of the whole circuit is 4.86 nW under a 0.9 V power supply at 27 o C. The estimated silicon area is 0.0012 mm 2 .

关键词： MOSFET Threshold voltage Topology Junctions Photonic band gap

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Electromechanical Properties of One Dimensinal Carbon Chains

Electromechanical Properties of One Dimensinal Carbon Chains

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IEEE International Conference on Nano/Molecular Medicine and Engineering

作者： Zeina Salman Arun Nair Steve Tung Microelectronics and Photonics Graduate Program University of Arkansas Fayetteville Arkansas 72701 USA Department of Mechanical Engineering University of Arkansas Fayetteville Arkansas 72701 USA

ISBN: (纸本)9781467396738

Carbon based nanostructures such as graphene and carbon nanotubes have received widespread attention due to their unique mechanical and electronic properties. This paper describes a quantum mechanics based study of the electronic band structures and transport properties of one-dimensional (1D) carbon chains, the thinnest nanowires available in nature. The study is based on the application of density functional theory and non-equilibrium Green's function where maximally localized Wannier functions and Landauer formalism are combined to compute the electronic band structures and quantum conductance of the 1D carbon chains. The simulation result indicates that the peak quantum conductance of 1D carbon chains is about five times smaller than that of carbon nanotubes. However, the quantum conductance is also a function of the length and chemical bonds of the carbon chains. When the carbon chains are mechanically strained at 3%, the quantum conductance is reduced by about 50%. This result suggests 1D carbon chains can provide ultra high-resolution electromechanical measurements of important biomolecules such as DNA.

关键词： Carbyne Chains First-principle simulation Localized Wannier Functions Quantum Conductance

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MOS-only M-2M DAC for ultra-low voltage applications

MOS-only M-2M DAC for ultra-low voltage applications

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Israel Sperotto Hamilton Klimach Sergio Bampi Microelectronics Graduate Program Federal University of Rio Grande do Sul Porto Alegre RS Brazil Electrical Engineering Department Federal University of Rio Grande do Sul Porto Alegre RS Brazil Informatics Institute Federal University of Rio Grande do Sul Porto Alegre RS Brazil

This work presents a study of the CMOS based R-2R ladder network (also called M-2M) Digital-to-Analog Converter (DAC) as a potential candidate for ultra-low voltage (ULV) applications, i.e. supply voltages VDD lower than 200mV. MOS transistors operate in subthreshold under such very low VDD, and the circuit analysis must be done using an all-region continuous MOSFET model. Simulation results in a commercial 130 nm process corroborate the presented analysis, showing that it is possible to implement this DAC topology for 6 to 8 bits operating under supply voltages from 70 mV to 140 mV.

关键词： MOSFET Semiconductor device modeling Analytical models Mathematical model CMOS integrated circuits Integrated circuit modeling

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