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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Caroline P. Garcia Bernardo Lourosa Gilson I. Wirth Graduate Program in Microelectronics (PGMicro) Universidade Federal do Rio Grande do Sul Porto Alegre Brazil Electrical Engineering Department (DELET) Universida de Federal do Rio Grande do Sul Porto Alegre Brazil

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

As transistors dimensions shrink to nanometer sizes, the variability of their electrical parameters becomes a significant factor in the performance of integrated circuits. Random Telegraph Noise (RTN) is a time-dependent variability that changes the drain current (or threshold voltage) of metal-oxide-semiconductor field-effect transistors (MOSFETs) from one instant in time to the other, leading to jitter in oscillating circuits, such as ring and voltage-controlled (VCO) oscillators. This work evaluates the time-domain jitter caused by the RTN in a capacitive and a current-controlled ring oscillator-based VCO. Different concepts of jitter (absolute jitter, period jitter, and cycle-to-cycle jitter) are studied, focusing on the influence of time window sizes on the jitter amplitude. Monte Carlo simulations are employed for both oscillators, considering a modified SPICE simulator to properly include the RTN impact on the threshold voltage of the transistors.

关键词： Ring oscillators Monte Carlo methods Voltage-controlled oscillators Noise Jitter SPICE Threshold voltage Transistors Autocorrelation Time-domain analysis

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Towards a Machine Learning Based Method for Indirect Test Generation of Mixed-Signal Circuits

Towards a Machine Learning Based Method for Indirect Test Ge...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Állan F. G. Ferreira Lucas B. Zilch Vinícius Navarro Marcelo S. Lubaszewski Tiago R. Balen Electrical Engineering Department Universidade Federal do Rio Grande do Sul Porto Alegre Brazil Graduate Program in Microelectronics - PGMICRO Universidade Federal do Rio Grande do Sul Porto Alegre Brazil

This work presents the proposal and feasibility evaluation of a machine learning (ML) based method for test generation of analog and mixed-signal circuits. The method first relies on the use of a previously proposed low-cost automatic test generation tool (based on spice simulation) to simulate the circuit specifications and low cost parametric measures (in this case, DC values of circuit nodes under different input stimuli). Variability data, based on Monte Carlo Simulation is also generated by the tool, by using an open source spice simulator and the appropriate foundry models of the transistors. With this dataset in hand, the method consists on training ML models to relate the low cost DC node measurements with the circuit specifications, configuring a well-known indirect test strategy. The models are evaluated and those with the best performance are selected, resulting in a set of low-cost measurements and ML algorithms that represent an indirect test strategy to predict the CUT tested specifications. The considered case study is a fully-differential integrated filter designed on a commercial 180 nm process. Results show a R 2 score equal to 0.76, 0.76 and 0.98 for the DC gain, cutoff frequency and slew rate parameters, respectively. A total of 19 indirect measurements were selected for performing the tests. Finally, the presented method facilitates the implementation of the indirect test in analog circuits. A wide range of design parameters can be explored, selecting those that best contribute to the quality of the indirect test.

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A Power-Efficient FFT Hardware Architecture Exploiting Approximate Adders

A Power-Efficient FFT Hardware Architecture Exploiting Appro...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Guilherme Ferreira Pedro T. L. Pereira Guilherme Paim Eduardo Costa Sergio Bampi Graduate Program in Microelectronics (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Brazil Graduate Program in Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Brazil

ISBN: (数字)9781728176703

ISBN: (纸本)9781728176710

This work presents an energy-efficient Fast Fourier Transform (FFT) hardware architecture exploiting approximate adder circuits. The FFT hardware architecture consists of a fixed-point fully sequential architecture with a radix-2 butterfly with decimation in time (DIT). In this paper, we explore a set of approximate adders (LOA, ETA-I, Copy-A, Copy-B, Trunc0, Trunc1) in the butterfly by varying the approximation level (K term). The Root-Mean-Square Error (RMSE) metric shows which approximate level term allows the FFT processing without widely signal losses. The results show that our best-proposed FFT employing Trunc0 approximate adder with K =10 saves up to 35% of power dissipation compared to the FFT with the original radix-2 butterfly using the synthesis tool operators.

关键词： Measurement Fast Fourier transforms Circuits and systems Hardware Energy efficiency Topology Power dissipation

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Boosting the Efficiency of the Harmonics Elimination VLSI Architecture by Arithmetic Approximations

Boosting the Efficiency of the Harmonics Elimination VLSI Ar...

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Patricia da Costa Pedro T. L. Pereira Guilherme Paim Eduardo da Costa Sergio Bampi Graduate Program in Microelectronics (PGMICRO) - Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil Graduate Program in Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil

Approximate computing emerged as a key alternative for trading off accuracy against energy efficiency and area reduction. Error-tolerant applications, such as multimedia processing, machine learning, and signal processing, can process the information with lower-than-standard accuracy at the circuit level while still fulfilling a good and acceptable service quality at the application level. Adaptive filtering-based systems have been demonstrating high resiliency against hardware errors due to their intrinsic self-healing characteristic. This paper investigates the design space exploration of arithmetic approximations in a Very Large-Scale Integration (VLSI) harmonic elimination (HE) hardware architecture based on Least Mean Square (LMS) adaptive filters. We evaluate the Pareto front of the area- and power versus quality curves by relaxing the arithmetic precision and by adopting both approximate multipliers (AxMs) in combination with approximate adders (AxAs). This paper explores the benefits and impacts of the Dynamic Range Unbiased (DRUM), Rounding-based Approximate (RoBA), and Leading one Bit-based Approximate (LoBA) multipliers in the power dissipation, circuit area, and quality of the VLSI HE architectures. Our results highlight the LoBA 0 as the most efficient AxM applied in the HE architecture. We combine the LoBA 0 with Copy and LOA AxAs with variations in the approximation level (L). Notably, LoBA 0 and LOA with $L=6$ resulted in savings of 43.7% in circuit area and 45.2% in power dissipation, compared to the exact HE, which uses multiplier and adder automatically selected by the logic synthesis tool. Finally, we demonstrate that the best hardware architecture found in our investigation successfully eliminates the contaminating spurious noise (i.e., 60 Hz and its harmonics) from the signal.

关键词： Power quality Computer architecture Very large scale integration Harmonic analysis Boosting Hardware Power dissipation

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The Impact of Hot Carrier Injection-Induced Device Degradation for Lower-Power FinFETs

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Journal of Electronic Materials 2023年第2期52卷 1391-1399页

作者： Chen, Yu-Lin Yeh, Wen-Kuan Hsu, Heng-Tung Chen, Ke-Horng Lien, Der-Hsien Lin, Wen-Chin Yu, Tien-Han Chiu, Yu-Sheng Godwinraj, D. Godfrey, D. Wu, Chien-Hung International College of Semiconductor Technology National Yang Ming Chiao Tung University Hsinchu Taiwan Graduate Degree Program of College of Electrical and Computer Engineering National Yang Ming Chiao Tung University Hsinchu Taiwan Institute of Electronics National Yang Ming Chiao Tung University Hsinchu Taiwan Institute of Microelectronics National Cheng Kung University Tainan Taiwan Department of ECE Amal Jyothi College of Engineering Kerala Kottayam India Department of Optoelectronics and Materials Engineering Chung Hua University Hsinchu Taiwan Department of Electronics and Communication Engineering Dayananda Sagar University Bengaluru India National Applied Research Laboratories Hsinchu Taiwan

The impact of hot carrier injection (HCI) on the performance of standard and low-VT FinFETs are investigated and benchmarked with each other. For this investigation, these FinFETs were fabricated with various gate lengths (L) from 16 to 36 nm. HCI-induced transconductance degradation in standard devices for gate length variations of 36 nm down to 16 nm was 75%, while it was 35% for low-VT devices. Similarly, the degradation of threshold voltage in standard devices for gate length variations of 36 nm down to 16 nm was 39%, while it was 36% for low-VT device. In this work, as the device is subject to HCI, we found that: (1) short-channel devices cause severe degradation on the threshold voltage and transconductance (gm) compared to long-channel devices, owing to the higher electric field for short-channel devices at the gate edge, (2) standard devices exhibit a more stable threshold voltage than that of low-VT power devices, since the TiN barrier layer prevents Al atom diffusion into the HfO2 layer, and (3) the transconductance efficiency of standard devices is better than that of low-VT power devices. Further, the lower-VT devices show lower transconductance degradation than standard devices. However, the transconductance degradation of the long-channel standard and low-VT devices are the same. Compared to short-channel low-VT devices, extended-channel standard devices are more immune to the HCI effect. © 2022, The Minerals, Metals & Materials Society.

关键词： Threshold voltage

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Coherent Acoustic Phonons in Bi2Se3 Ultrathin Films Probed by Femtosecond, Optical Pump-Probe Spectroscopy

Coherent Acoustic Phonons in Bi2Se3 Ultrathin Films Probed b...

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CLEO: Fundamental Science, CLEO:FS 2024 - Part of Conference on Lasers and Electro-Optics, CLEO 2024

作者： Cheng, Jing Niherysh, Kiryl A. Francis, Peter Chakraborty, Debamitra Lombardi, Floriana Erts, Donats Prischepa, Serghej L. Laszcz, Adam Komissarov, Ivan V. Sobolewski, Roman Materials Science Graduate Program University of Rochester RochesterNY14627 United States Laboratory for Laser Energetics University of Rochester RochesterNY14623-1299 United States Department of Microtechnology and Nanoscience Chalmers University of Technology Gothenburg Sweden Institute of Chemical Physics University of Latvia Riga Latvia Department of Electrical and Computer Engineering University of Rochester RochesterNY14627 United States Dipartimento di Fisica "E.R. Caianiello" Università degli Studi di Salerno Sa FiscianoI-84084 Italy Lukasiewicz Research Network Institute of Microelectronics and Photonics WarszawaPL-02668 Poland

ISBN: (纸本)9781957171395

The dynamics of coherent acoustic phonons in the Bi2Se3 layered crystal system are investigated. The findings reveal that the frequency evolution of breathing modes with the number of the material quintuple layers and the dispersion relation both can be explained by a modified chain model with a nonuniform coupling force. © Optica Publishing Group 2024, © 2024 The Author(s)

关键词： Ultrathin films

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A 40 nW 32.7 kHz CMOS Relaxation Oscillator with Comparator Offset Cancellation for Ultra-Low Power applications

A 40 nW 32.7 kHz CMOS Relaxation Oscillator with Comparator ...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： William Teles Medeiros Hamilton Klimach Sergio Bampi Microelectronics Graduate Program UFRGS Porto Alegre RS Brazil

ISBN: (数字)9781728134277

ISBN: (纸本)9781728134284

This paper presents a fully-integrated 32.7 kHz relaxation oscillator designed in TSMC 40 nm CMOS for IoT applications. Simulation results show that the proposed relaxation oscillator consumes 40 nW at room temperature from 0.6 V power supply. The architecture achieves a temperature coefficient (TC) as low as 12.5 ppm/°C (μ = 35.5 ppm/°C for 400 samples) from -40°C to 125°C. Also, more than 50% of samples have a TC less than 30 ppm/°C. The oscillator also has a fast start-up time, achieving a steady-state of the operating frequency within 3 cycles. The energy efficiency is 1.22 nW/kHz, and the entire circuit occupies an active area of 0.127 mm 2 .

关键词： Oscillators Temperature sensors Power demand Switches Capacitors Low-power electronics Tunneling

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NIR-Responsive Methotrexate-Modified Iron Selenide Nanorods for Synergistic Magnetic Hyperthermic, Photothermal, and Chemodynamic Therapy

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ACS Applied Materials and Interfaces 2024年第20期16卷 25622-25636页

作者： Thirumurugan, Senthilkumar Muthiah, Kayalvizhi Samuvel Lin, Yu-Chien Dhawan, Udesh Liu, Wai-Ching Wang, An-Ni Liu, Xinke Hsiao, Michael Tseng, Ching-Li Chung, Ren-Jei No. 1 Section 3 Zhongxiao East Road Taipei10608 Taiwan Centre for the Cellular Microenvironment Division of Biomedical Engineering James Watt School of Engineering Mazumdar-Shaw Advanced Research Centre University of Glasgow GlasgowG116EW United Kingdom Faculty of Science and Technology Technological and Higher Education Institute of Hong Kong Hong Kong New Territories999077 Hong Kong Scrona AG Grubenstrasse 9 Zürich8045 Switzerland College of Materials Science and Engineering Chinese Engineering and Research Institute of Microelectronics Shenzhen University Shenzhen518060 China Department of Electrical and Computer Engineering National University of Singapore Singapore117583 Singapore Genomics Research Center Academia Sinica Taipei115 Taiwan Department and Graduate Institute of Veterinary Medicine School of Veterinary Medicine National Taiwan University Taipei10617 Taiwan Graduate Institute of Biomedical Materials and Tissue Engineering College of Biomedical Engineering Taipei Medical University Taipei11031 Taiwan International Ph.D. Program in Biomedical Engineering College of Biomedical Engineering Taipei Medical University Taipei11031 Taiwan Research Center of Biomedical Device College of Biomedical Engineering Taipei Medical University Taipei11031 Taiwan International Ph.D. Program in Cell Therapy and Regenerative Medicine College of Medicine Taipei Medical University Taipei11031 Taiwan Taipei10608 Taiwan

Breast cancer is a malignant tumor with a high mortality rate among women. Therefore, it is necessary to develop novel therapies to effectively treat this disease. In this study, iron selenide nanorods (FeSe2 NRs) were designed for use in magnetic hyperthermic, photothermal, and chemodynamic therapy (MHT/PTT/CDT) for breast cancer. To illustrate their efficacy, FeSe2 NRs were modified with the chemotherapeutic agent methotrexate (MTX). MTX-modified FeSe2 (FeSe2-MTX) exhibited excellent controlled drug release properties. Fe2+ released from FeSe2 NRs induced the release of •OH from H2O2 via a Fenton/Fenton-like reaction, enhancing the efficacy of CDT. Under alternating magnetic field (AMF) stimulation and 808 nm laser irradiation, FeSe2-MTX exerted potent hyperthermic and photothermal effects by suppressing tumor growth in a breast cancer nude mouse model. In addition, FeSe2 NRs can be used for magnetic resonance imaging in vivo by incorporating their superparamagnetic characteristics into a single nanomaterial. Overall, we presented a novel technique for the precise delivery of functional nanosystems to tumors that can enhance the efficacy of breast cancer treatment. © 2024 The Authors. Published by American Chemical Society

关键词： Magnetic resonance imaging

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RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32

RISC-V SoC Physical Implementation in 180 nm CMOS with a Qua...

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IEEE Ecuador Technical Chapters Meeting (ETCM)

作者： Felipe F. Nascimento Rodrigo N. Wuerdig André F. Ponchet Bruno Sanches Denis S. Loubach Roberto D’Amore Marcus H. Victor Junior Walter S. Oliveira Vitor O. Kuribara Luiz C. Moreira Electronic Engineer Division IEEA Aeronautics Institute of Technology São José dos Campos Brazil Graduate Program on Microelectronics UFRGS Porto Alegre Brazil Department of Electronic Systems University of São Paulo São Paulo Brazil Department of Computer Systems Aeronautics Institute of Technology São José dos Campos Brazil

This article presents the first known physical implementation of a RISC-V core based on the FemtoRV32 project, using the Quark core to implement the RV32I instruction set. Our primary goal is to validate the micro-architecture for ASIC development. Implemented using 180 nm CMOS technology, the core demonstrates functionality at frequencies as high as 120 MHz, which represents a 150% improvement over FPGA implementations. Power dissipation tests estimate a range of 68 to 108 mW, under different PVT corners, and slack margins of 0.5 and 2 ps, respectively. The core also passed standard regression tests for RISC-V ISA compliance, executed within an automated verification environment. Additionally, our paper outlines the ASIC implementation tools and methodologies employed, adding to its viability as a foundation for developing low-cost microprocessors or custom ASICs for specific applications.

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Hardware Architecture for the Regular Interpolation Filter of the AV1 Video Coding Standard

Hardware Architecture for the Regular Interpolation Filter o...

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European Signal Processing Conference (EUSIPCO)

作者： Daiane Freitas Rafael da Silva Ícaro Siqueira Cláudio M. Diniz Ricardo A. L. Reis Mateus Grellert Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil Graduate Program on Microelectronics Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil Embedded Computing Lab Federal University of Santa Catarina (UFSC) Florianopólis Brazil

ISBN: (数字)9789082797053

ISBN: (纸本)9781728150017

This work proposes a hardware architecture for fractional-pixel interpolation filter defined in the royalty-free AV1 video coding standard. Analysis conducted in this work shows that the AV1 Regular family of filters has the highest usage especially when considering high resolution videos. The proposed architecture implements the 15 interpolation filters of the AV1 Regular family and is capable to interpolate videos of up to 8K video resolution at 120 fps. The proposed architecture achieves the highest throughput compared to related works.

关键词： Video coding Interpolation Computer architecture Parallel processing Filtering algorithms Hardware Standards

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