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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： David Cordova Pedro Toledo Hamilton Klimach Sergio Bampi Eric Fabris Graduate Program on Microelectronics UFRGS Porto Alegre RS Brazil

Electromagnetic Interference (EMI) degrades the performance of voltage and current references, due to its finite Power Supply Rejection Ratio (PSRR). The design of a 90 dB PSRR, 4 dBm EMI resistant MOSFET-Only Voltage Reference is herein presented. The Voltage Reference is designed based on the Zero Temperature Coefficient (ZTC) transistor point. The high-PSRR is obtained using zero-V T transistors as active loads in the open and feedback loop of the circuit. The final circuit was designed in a 130 nm CMOS process and occupies around 0.014 mm 2 of silicon area while consuming just 1.15 μW. Postlayout simulations present a 206 mV of Voltage Reference with a Temperature Coefficient of 321 ppm/° C, for the temperature range from -55 to 125 ° C. An EMI source of 4 dBm (1 V pp ) injected in the power supply, according to the Direct Power Injection (DPI) standard, yield in a maximum DC Shift and Peak-to-Peak ripple of -0.17 % and 822 μV pp , respectively.

关键词： Electromagnetic interference Transistors Power supplies Logic gates Resistance Temperature distribution Threshold voltage

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AxRSU- : Higher-Order m-Bit Approximate Encoders for Radix- Squarer Units

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Circuits, Systems, and Signal Processing 2024年第6期43卷 1-30页

作者： da Rosa, Morgana M. A. Paim, Guilherme da Costa, Eduardo A. C. Soares, Rafael Bampi, Sergio Graduate Program on Computing Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program in Microelectronics Federal University of RGS Porto Alegre Brazil Graduate Program in Electronics and Computer Engineering Catholic University of Pelotas Pelotas Brazil

Approximate computing has emerged as a design alternative to enhance design efficiency by capitalizing on the inherent error resilience observed in numerous applications. Various error-resilient and compute-intensive applications, such as signal, image and video processing, computer vision, and supervised machine learning, necessitate dedicated hardware accelerators for mean squared error estimation during runtime. In these application domains, using efficient arithmetic operators, particularly a squarer unit, represents one of the most effective strategies for low-power design. This work introduces an approximate Radix- $$2^{m}$$ squarer unit, denoted as AxRSU- $$2^{m}$$ . The proposed squarer unit employs m-bit approximate encoders to execute operations on m-bit data concurrently. The AxRSU- $$2^{m}$$ under consideration explores encoders with m equal to 2 (AxRSU-4), 3 (AxRSU-8), and 4 (AxRSU-16). These approximate encoders exhibit low complexity and diminish the necessary partial products operating on m bits simultaneously, thereby substantially enhancing energy efficiency and reducing circuit area in the AxRSU- $$2^{m}$$ . To illustrate the trade-off between error and quality in the AxRSU- $$2^{m}$$ , we apply it to an SSD (sum squared difference) hardware accelerator designed for video processing, with a square-accumulate serving as a case study. Our findings reveal a novel Pareto front, presenting eight optimal AxRSU- $$2^{m}$$ solutions that achieve accuracy levels ranging from 3.76 to 75.53%. These solutions yield energy savings ranging from 46.20 to 95.57% and circuit area reductions ranging from 37.68 to 66.73%.

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A 40 nW 32.7 kHz CMOS Relaxation Oscillator with Comparator Offset Cancellation for Ultra-Low Power applications

A 40 nW 32.7 kHz CMOS Relaxation Oscillator with Comparator ...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： William Teles Medeiros Hamilton Klimach Sergio Bampi Microelectronics Graduate Program UFRGS Porto Alegre RS Brazil

ISBN: (数字)9781728134277

ISBN: (纸本)9781728134284

This paper presents a fully-integrated 32.7 kHz relaxation oscillator designed in TSMC 40 nm CMOS for IoT applications. Simulation results show that the proposed relaxation oscillator consumes 40 nW at room temperature from 0.6 V power supply. The architecture achieves a temperature coefficient (TC) as low as 12.5 ppm/°C (μ = 35.5 ppm/°C for 400 samples) from -40°C to 125°C. Also, more than 50% of samples have a TC less than 30 ppm/°C. The oscillator also has a fast start-up time, achieving a steady-state of the operating frequency within 3 cycles. The energy efficiency is 1.22 nW/kHz, and the entire circuit occupies an active area of 0.127 mm 2 .

关键词： Oscillators Temperature sensors Power demand Switches Capacitors Low-power electronics Tunneling

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Within-die and die-to-die variability on 65nm CMOS : Oscillators experimental results 6

Within-die and die-to-die variability on 65nm CMOS : Oscilla...

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6th International Workshop on CMOS Variability, VARI 2015

作者： Brito, Juan Pablo Martinez Lubaszewski, Marcelo Bampi, Sergio Graduate Program on Microelectronics PGMICRO - Informatics Institute Federal University of Rio Grande do Sul UFRGS Porto Alegre Brazil CEITEC S.A. Semiconductors Porto Alegre Brazil

ISBN: (纸本)9781509000715

This paper presents experimental data and analyses from the oscillation frequency of CMOS ring oscillators (ROs). The measurements are analyzed in order to separate the coefficient of variation (CV = σ/μ) behavior of both within-die (WID) process variations and Die-to-Die (D2D) process variations. Three different RO's sizes distributed over a total of 96 ROs per chip were measured in 32 different chip samples, all from a single MOSIS Multi-Project-wafer in a commercial 65nm CMOS process. All ROs were measured with varying power supply voltages, from nominal VDD (1.2V) down to nearthreshold (0.45V), resulting in a sample space of 18.432 points of interest. Statistical analysis results are shown regarding each RO stage size, the applied power supply and the correlation of both to the WID and D2D variations. The increase on D2D and WID coefficients of variations at the near-threshold supplies is very significant, as explained by increased delay variability at the moderate inversion regime of the FETs. The 96 test ROs occupy a total area of 200 x 480 μm2 in each test chip. © 2015 IEEE.

关键词： Dies

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MOSFET stacked-pair test structure for mismatch evaluation by estimating the on-resistance ratio 6

MOSFET stacked-pair test structure for mismatch evaluation b...

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6th International Workshop on CMOS Variability, VARI 2015

作者： Brito, Juan Pablo Martinez Lubaszewski, Marcelo Bampi, Sergio Graduate Program on Microelectronics PGMICRO - Informatics Institute Federal University of Rio Grande do Sul - UFRGS Porto Alegre Brazil CEITEC S.A. Semiconductors Porto Alegre Brazil

ISBN: (纸本)9781509000715

This work describes a procedure for evaluating the mismatch between MOSFET transistors in a test array and connected as stacked-pairs. The transistor mismatch is characterized by measuring the gate voltage dependence of the DC voltage established at the middle node of the common-gate MOSFET stacked-pair. This procedure is modeled as the onresistance ratio of these two transistors and it is performed by two simple measurements. Various pieces of information on the MOSFET mismatch characteristics (e.g., channel length variation and threshold voltage variation) can be extracted. The test structure was manufactured in 180nm CMOS technology, and the test array was designed to allow a large number of MOSFET stacked-pairs, from transistors placed in different parts of the layout to vary gradually the distance of the paired FETs. © 2015 IEEE.

关键词： Threshold voltage

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EMI resisting MOSFET-Only Voltage Reference based on the ZTC condition

EMI resisting MOSFET-Only Voltage Reference based on the ZTC...

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Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)

作者： David Cordova Pedro Toledo Hamilton Klimach Sergio Bampi Eric Fabris NSCAD Microeletronica Graduate Program on Microelectronics UFRGS Porto Alegre RS Brazil

Electromagnetic interference (EMI) can significantly degrade the performance of analog circuits, including DC voltage and current references, due to their limited Power Supply Rejection Ratio (PSRR). An EMI-resisting MOSFET-Only Voltage Reference is herein proposed, based on the MOSFET Zero Temperature Coefficient (ZTC) vicinity condition. The ZTC condition is analytically derived through a continuous MOSFET model that is valid from weak to strong inversion and a design methodology is proposed. The final circuit was designed in a 130 nm process and occupies around 0.0075 mm 2 of silicon area while consuming just 10.3 μW. Post-layout simulations presented a Voltage Temperature Coefficient (VTC) of 146 ppm/°C, for a temperature range from -55 to +125°C. An EMI source of 4 dBm (1 Vp P amplitude) injected in the power supply of our circuit, according to the Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of 22.7 % and 11m Vpp, respectively.

关键词： Electromagnetic interference MOSFET Temperature dependence Power supplies Logic gates Semiconductor device modeling

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A 0.7V Fully Differential First Order GZTC-C filter

A 0.7V Fully Differential First Order GZTC-C filter

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Pedro Toledo Renê Timbo David Cordova Hamilton Klimach Sergio Bampi Eric Fabris NSCAD Microeletronica Graduate Program on Microelectronics-UFRGS Porto Alegre RS Brazil

A 0.7 V supply voltage fully differential first order GZTC-C filter is herein proposed. The GZTC-C filter definition is used in this paper as a Transconductance-Capacitor filter (Gm-C) in which its gm stage is biased exactly on transconductance zero-temperature (GZTC) bias condition. This special bias point has all necessary conditions to design MOSFET transconductors with low temperature dependence. Additionally, two calibrate-points with three-bit resolution have been added to mitigate process variations which may cause bias shift errors on sensitive nodes, driving the circuit out of its normal GZTC operation region. The final circuit has been designed in a 130 nm CMOS process generating a 5 MHz cutoff frequency. The filter occupies around 0.01 mm 2 of silicon area while consuming just 21 μW. Monte Carlo (MC) post-layout and post-calibrated simulation has presented an Effective Cutoff Frequency Temperature Co-efficient (TC eff ) average of 73.4 ppm/°C with 30.6 ppm/°C standard deviation for a temperature range from -40 to +120°C and has estimated a cutoff frequency fabrication sensitivity of σ/μ = 0.87%, including average process and local mismatch variability.

关键词： MOSFET Temperature dependence Transconductance Temperature sensors Semiconductor device modeling Threshold voltage

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A fully integrated CMOS 2.4GHz and 24dBm linear power amplifier

A fully integrated CMOS 2.4GHz and 24dBm linear power amplif...

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Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)

作者： Gabriel Teófilo Neves Guimarães Hamilton Duarte Klimach Sergio Bampi Microelectronics Graduate Program Federal University of Rio Grande do Sul Porto Alegre RS BR Microelectronics Graduate Program Federal University of Rio Grande do Sul Porto Alegre RS Brazil

This work presents a fully integrated single-stage 2.4 GHz power amplifier (PA) that was designed in a 180nm CMOS process using a power combining technique to achieve higher output power. A series combining transformer (SCT) combines two cascode differential amplifiers and makes extensive use of virtual AC ground nodes to reduce the impact of bond-wire parasitics. The center-taps of the output transformers are used for 2nd harmonic impedance tuning inside the chip. In post-layout simulation the PA uses a 3.3 V power supply and achieves 24dBm maximum output power at a peak drain efficiency of 23.4%. The test chip returned recently from fabrication and it will undergo electrical tests soon.

关键词： Transistors Power generation Impedance Layout Capacitors Power amplifiers Standards

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Expanding chiral metamaterials for retrieving fingerprints via vibrational circular dichroism

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Light(Science & Applications) 2023年第7期12卷 1401-1414页

作者： Cheng Xu Zhihao Ren Hong Zhou Jingkai Zhou Chong Pei Ho Nan Wang Chengkuo Lee Department of Electrical and Computer Engineering National University of SingaporeSingapore 117583Singapore Center for Inteligent Sensors and MEMS(CISM) National University of SingaporeSingapore 117608Singapore institute of Microelectronics(IME) Agency for ScienceTechnology and Research(A*STAR)Singapore 138634Singapore NUS Graduate School for Integrative Science and Engineering Program(ISEP) National University of SingaporeSingapore 117456Singapore

Circular dichroism(CD)spectroscopy has been widely demonstrated for detecting chiral ***,the determination of chiral mixtures with various concentrations and enantiomeric ratios can be a challenging *** solve this problem,we report an enhanced vibrational circular dichroism(VCD)sensing platform based on plasmonic chiral metamaterials,which presents a 6-magnitude signal enhancement with a selectivity of chiral *** by coupled-mode theory,we leverage both in-plane and out-of-plane symmetry-breaking structures for chiral metamaterial design enabled by a two-step lithography process,which increases the near-field coupling strengths and varies the ratio between absorption and radiation loss,resulting in improved chiral light-matter interaction and enhanced molecular VCD ***,we demonstrate the thin-film sensing process of BSA andβ-lactoglobulin proteins,which contain secondary structures a-helix andβ-sheet and achieve a limit of detection down to zeptomole ***,we also,for the first time,explore the potential of enhanced VCD spectroscopy by demonstrating a selective sensing process of chiral mixtures,where the mixing ratio can be successfully differentiated with our proposed chiral *** findings improve the sensing signal of molecules and expand the extractable information,paving the way toward label-free,compact,small-volume chiral molecule detection for stereochemical and clinical diagnosisapplications.

关键词： chiral vibrational circular

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A comparative study between FinFET and CMOS-based SRAMs under resistive defects 20

A comparative study between FinFET and CMOS-based SRAMs unde...

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20th IEEE Latin American Test Symposium, LATS 2019

作者： Copetti, T.S. Balen, T.R. Brum, E. Aquistapace, C. Poehls, L. Bolzani Graduate Program on Microelectronics-PGMICRO Universidade Federal Do Rio Grande Do sul Porto Alegre Brazil School of Engineering Pontifical Catholic University of Rio Grande Do sul Porto Alegre Brazil

ISBN: (纸本)9781728117560

Due to several factors, such as Process Variations (PV), increased leakage current, Random Dopant Fluctuation (RDF), and mainly the Short-Channel Effect (SCE), the miniaturization of planar CMOS transistors reached its limit at the 22nm node. To continue the miniaturization process via technology down-scaling, while preserving system reliability and performance, FinFET devices arise as an alternative to substitute the CMOS transistors. Additionally, Static Random-Access Memories (SRAMs) have been increasingly occupying a great part of Systems-on-Chips (SoCs) silicon area. Designed to reach densities at the limit of the manufacturing process, make this component susceptible to manufacturing defects, including resistive defects. Such defects can escape traditional manufacturing tests, because they may cause dynamic faults during circuits' lifetime. In this context, a comparison between a 20nm FinFET-based SRAM block and a commercial 65nm CMOS-based SRAM block focusing on resistive defects is carried out. The behavior of defective cells operating over different temperature sets has been investigated by means of SPICE simulations. Results show an expressively higher occurrence of dynamic faults induced by resistive defects in FinFET-based memories when compared to CMOS technology. © 2019 IEEE.

关键词： Defects

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