检索结果-内蒙古大学图书馆

Ξ hypernuclei CΞ15 and BeΞ12, and the ΞN two-body interaction

Physical Review C 2022年第4期105卷 044324-044324页

作者： Yusuke Tanimura Hiroyuki Sagawa Ting-Ting Sun Emiko Hiyama Department of Physics Tohoku University Sendai 980-8578 Japan Graduate Program on Physics for the Universe Tohoku University Sendai 980-8578 Japan Center for Mathematics and Physics the Univeristy of Aizu Aizu-Wakamatsu Fukushima 965-8580 Japan RIKEN Nishina Center Wako Saitama 351-0198 Japan School of Physics and Microelectronics Zhengzhou University Zhengzhou 450001 China

We study the energy spectra of Ξ hypernuclei CΞ15 and BeΞ12 with a relativistic mean field (RMF) model with meson exchange ΞN interactions. The RMF parameters are optimized to reproduce the average energy of KINKA and IRRAWADDY events for the ground state and also the average energy of KISO and IBUKI events for the excited state in CΞ15. The potential depth of the average ΞN mean field potential is found to be about −12 MeV in the nuclear matter limit. We further introduce the two-body s- and p-wave interactions between valence nucleons and Ξ particle. We found that the s-wave interaction deduced from the HAL lattice QCD results is rather weak to obtain the energy difference between IRRAWADDY and KINKA events. The p-wave interaction is added and fitted to reproduce the energy difference. The resulting interaction together with the s-wave one gives a reasonable energy simultaneously for IBUKI event as an excited Ξp state. The model is further applied to predict the energy spectrum of BeΞ12.

关键词： Binding energy & masses Nuclear structure & decays

来源：评论

学校读者我要写书评

暂无评论

Combining m=2 Multipliers and Adder Compressors for Power Efficient Radix-4 Butterfly

Combining m=2 Multipliers and Adder Compressors for Power Ef...

引用

Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Guilherme Ferreira Leandro M. G. Rocha Eduardo Costa Sergio Bampi Graduate Program in Microelectronics (PGMICRO) - Federal University of Rio Grande do Sul (UFRGS) Brazil Graduate Program in Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Brazil

ISBN: (数字)9781728180588

ISBN: (纸本)9781728180595

In this work, we propose a power-efficient hardware architecture for 16-bit m Radix-4 DIT (Decimation in Time) butterfly using radix-2 m multipliers, with m=2, and 4-2 adder compressors. The multiplier uses both Wallace and Dadda schemes in the addition tree, with Carry-Select, Kogge Stone, and '+' operator from the tool internally. We used a method for a realistic power extraction with the standard delay format. The results show that our best-proposed Radix-4 butterfly saves up to 25% of power dissipation when compared with the original Radix-4 butterfly using the synthesis tool operators for both adders and multipliers. The optimized structure combines the m=2 Wallace-based multiplier, employing Kogge-Stone adder into its addition tree, and 4-2 adder compressors.

关键词： Adders Compressors Tools Computer architecture Power dissipation Capacitance Libraries

来源：评论

学校读者我要写书评

暂无评论

Characterization of Enclosed Layout Transistors for Analog Applications on a130nm Technology

Characterization of Enclosed Layout Transistors for Analog A...

引用

Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Gustavo P. Platcheck Guilherme S. Cardoso Tiago R. Balen Graduate Program on Microelectronics-PGMICRO UFRGS Porto Alegre Brazil Department of Electronic IFSul Pelotas Brazil

ISBN: (数字)9781728196251

ISBN: (纸本)9781728196268

Enclosed Layout Transistors (ELT) comprise a feasible design alternative to hardening CMOS circuits against total ionizing dose effects. This design technique significantly reduces the leakage paths produced by trapped charges in the field oxide of regular NMOS devices. This work presents the characterization of several ELT devices designed and fabricated on a 130nm technology aiming at analog applications. Standard (rectangular) transistors with equivalent aspect ratio were also considered for comparison. The experimental data are compared with simulations performed using a commercial design tool, considering the aspect ratio (W/L) extracted from the layout. ELTs with the drain designed both as the inner and outer terminal were characterized and compared. Additionally, in order to improve the achievable aspect ratio range of the square ELTs, parallel and series associations of enclosed devices were implemented as well. According to obtained results, there may be significant differences between the W/L extracted from the design tool and its actual value in the fabricated device. For all enclosed devices, the simulation overestimates the current values. A different pattern regarding the influence of drain location (inner or outer terminal) on current performance is also observed when comparing measured data with simulations. Additionally, associations of ELT showed to be feasible to widen the range of possible aspect ratio of this particular transistor.

关键词： Transistors Mathematical model Logic gates Layout Data models Performance evaluation Tools

来源：评论

学校读者我要写书评

暂无评论

Optimizing Iterative-based Dividers for an Efficient Natural Logarithm Operator Design

Optimizing Iterative-based Dividers for an Efficient Natural...

引用

IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Patrícia Ücker Miguel R. Weirich Guilherme Paim Eduardo A. C. da Costa Sergio Bampi Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Brazil Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Brazil

ISBN: (数字)9781728134277

ISBN: (纸本)9781728134284

This work proposes to optimize iterative-based dividers for a natural logarithm operator design. The logarithm operator approximates the function at the base e. Such an operator is implemented using Taylor Series approximation. In this approximation, the division is a costly operation. In this work, we explore two iterative-based divider circuits for logarithm operator. We also offer an algorithm responsible for allowing input values different from the ones in the convergence region of the Taylor Series, with a reduced number of iterations. Through co-simulation using both the Matlab ® and ModelSim ® softwares, it was possible to determine the approximation quality of the implemented circuits, with a curve response very close to the Matlab one. Moreover, the Goldschmidt divider presents a slightly fewer relative error, mainly for higher input values comparing with Newton-Raphson. Synthesis results show that although the logarithm circuit with Newton-Raphson divider has marginally more area, it is more power-efficient than the one using Goldschmidt divider.

关键词： Approximation algorithms Taylor series Mathematical model Newton method Convergence Hardware Matlab

来源：评论

学校读者我要写书评

暂无评论

Ultra-Low Power Relaxation Oscillators survey: Design Trends and Challenges

Ultra-Low Power Relaxation Oscillators survey: Design Trends...

引用

PhD Research in microelectronics and Electronics Latin America (PRIME-LA)

作者： William Teles Medeiros Hamilton Klimach Sergio Bampi Microelectronics Graduate Program - UFRGS - Porto Alegre RS Brazil UFRGS - Porto Alegre RS Brazil

ISBN: (数字)9781728131467

ISBN: (纸本)9781728131474

The Relaxation oscillators (ROSCs) offer a better trade-off between power consumption, physical area and accuracy. This paper presents a study of recently published ultra-low-power relaxation oscillators with low-temperature coefficient, identifying its characteristics, performance parameters, and main challenges. A brief review show as state-of-the-art circuits handle with PVT (Process, voltage, and temperature) variations. By the end of this analysis, some trends in relaxation oscillators design are discussed.

关键词： Oscillators Capacitors Delays Resistors Power demand Switches Temperature sensors

来源：评论

学校读者我要写书评

暂无评论

An Efficient NLMS-based VLSI Architecture for Robust FECG Extraction and FHR Processing

An Efficient NLMS-based VLSI Architecture for Robust FECG Ex...

引用

IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Patrícia U. L. da Costa Guilherme Paim Leandro Rocha Eduardo da Costa Sérgio Almeida Sergio Bampi Graduate Program on Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Brazil Graduate Program on Microelectronics (PGMicro) - Federal University of Rio Grande do Sul (UFRGS) Brazil

ISBN: (数字)9781728160443

ISBN: (纸本)9781728160450

This work presents an efficient NLMS-based VLSI architecture to extract the fetal electrocardiogram (FECG) and detect the fetal heart rate (FHR), using the adaptive filter strategy. The efficient NLMS-based architecture herein investigated can robustly cancel the high-noised mother-related ECG signals, enabling the FHR measurement. We used the Improved Fetal Pan and Tompkins Algorithm (IFPTA) to detect fetal R-peak and calculate the FHR. Our NLMS-based VLSI architecture effectively detects the R-peaks in the extracted FECG with 93.2% accuracy with the only 2.4 mW of total power dissipation.

关键词： Fetal heart rate Very large scale integration Computer architecture Electrocardiography Hardware Thorax Power dissipation

来源：评论

学校读者我要写书评

暂无评论

Exploring NLMS and IPNLMS Adaptive Filtering VLSI Hardware Architectures for Robust EEG Signal Artifacts Elimination

Exploring NLMS and IPNLMS Adaptive Filtering VLSI Hardware A...

引用

IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Andrei La Rosa Patrícia Ucker Guilherme Paim Eduardo da Costa Sérgio Almeida Sergio Bampi Graduate Program on Computing Federal University of Pelotas (UFPel) Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Brazil Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Brazil

ISBN: (数字)9781728160443

ISBN: (纸本)9781728160450

The elimination of artifacts is a crucial procedure to extract the full potential of the information into the EEG processing. Embedded systems require low circuit area (cost) and efficient hardware architectures. Adaptive filtering plays a vital role as a single method and hybrid approaches for robustly eliminating the noise of the real-world EEG measures. In this paper, we propose and implement hardware architectures for both NLMS and IPNLMS adaptive filters. We investigate the filtering performance and circuit area, timing, and power dissipation of the hardware architecture proposals. To leverage the power-efficiency, we improve our hardware architectures employing the data-gating circuit design technique, which provided up to 20% power savings. Also, applying an HDL-Simulink co-simulation, we perform the hardware architectures tradeoff comparing the synthesis results and filtering performance. Our investigation demonstrates that IPNLMS reduces the time domain error in 11%, increasing less than 1% of circuit area and about the double of the energy per operation, compared to the NLMS.

关键词： Electroencephalography Hardware Computer architecture Convergence Measurement Clocks Proposals

来源：评论

学校读者我要写书评

暂无评论

Hot Carrier Injection Reliability of Fabricated N- and P-Type Multi FinFETs with Different TiN Stacks

引用

ECS Journal of Solid State Science and Technology 2023年第3期12卷 035007-035007页

作者： Chen, Yu-Lin Yeh, Wen-Kuan Hsu, Heng-Tung Chen, Ke-Horng Lin, Wen-Chin Yu, Tien-Han Chou, Hung-Ting Godwin Raj, D. Godfrey, D. International College of Semiconductor Technology National Yang Ming Chiao Tung University Taiwan Graduate Degree Program of College of Electrical and Computer Engineering National Yang Ming Chiao Tung University Taiwan National Applied Research Laboratories Taiwan Institute of Microelectronics National Cheng Kung University Taiwan National Chung-Shan Institute of Science and Technology Taoyuan Taiwan Dept of ECE Amal Jyothi College of Engineering Kerala India Dept of Electronics and Communication Engineering Dayananda Sagar University Bengaluru India

Device degradation due to hot carrier injection (HCI) in multi-fin 20 nm and 10 nm N- and P-type FinFET devices are thoroughly analyzed. To further understand the HCI reliability of the four FinFET devices, the device is fabricated with a standard Vt base and low Vt base gate stacks with different work functions. It is evident that: (i) The standard Vt device sustains lower effective stress bias due to the difference in threshold voltage, resulting in a more stable threshold voltage than the low Vt base device, and (ii) the transconductance of the single N- and P-type FinFET is more severely degraded than the multi-fin N- and P-type FinFET, mainly because multi N- and P-type Finfet has coupe effect, which effectively reduces the impact of HCI. © 2023 The Electrochemical Society ("ECS"). Published on behalf of ECS by IOP Publishing Limited

关键词： FinFET

来源：评论

学校读者我要写书评

暂无评论

Low-Voltage Dynamic Comparator with Bulk-Driven Floating Inverter Amplifier

Low-Voltage Dynamic Comparator with Bulk-Driven Floating Inv...

引用

Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Bruno Canal Hamilton D. Klimach Sergio Bampi Tiago R. Balen PGMicro - Graduate Program on Microelectronics Federal University of Rio Grande do Sul Porto Alegre RS Brazil

ISBN: (数字)9781728196251

ISBN: (纸本)9781728196268

This work presents a low voltage dynamic comparator for low-power ADC applications. The dynamic comparator uses a pre-amplifier powered by a floating reservoir capacitor and bulk-driven structure. The latch stage is done by a simple circuit to reduce the total voltage overhead necessary to define the logic levels and uses a charge sharing technique in order to reduce the energy consumption per conversion. The floating reservoir capacitor powered pre-amplifier reduces the impacts of global process variability and improves the input common-mode voltage performance. The bulk-driven structure lowers the threshold voltages of the pre-amplifier transistors at the sampling phase. Such structure also works as a positive feedback signal during the comparison phase to provide extra transconductance. The proposed dynamic comparator is designed and simulated in 28nm CMOS technology and reaches a performance suitable for 8 bits ADCs working with 600mV power supply. The dynamic comparator achieves 380μV input-referred noise, while consuming only 40 fJ per comparison and having a nominal delay of 2.26ns.

关键词： Latches Inverters Transistors Topology Transconductance Capacitors Reservoirs

来源：评论

学校读者我要写书评

暂无评论

Optimizing the Montgomery Modular Multiplier for a Power- and Area-Efficient Hardware Architecture

Optimizing the Montgomery Modular Multiplier for a Power- an...

引用

Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Mateus Terribele Leme Guilherme Paim Leandro M. G Rocha Patricia Ücker Vitor G. Lima Rafael Soares Eduardo A. C. da Costa Sergio Bampi Graduate Program in Microelectronics (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Graduate Program on Computer Science (PPGC) Federal University of Pelotas (UFPel)

ISBN: (数字)9781728180588

ISBN: (纸本)9781728180595

Cryptography hardware design is a key challenge towards the confidentiality advance in the prominent field of the internet of things (IoT). The rise of IoT embedded devices boosts the demand for power- and area- efficient solutions for cryptography hardware. The higher the robustness of the cryptography algorithm is, the higher are the hardware complexity, the circuit area, and energy consumption. Asymmetric algorithms are a particular class widely employed in ultra-secure cryptosystems. The high time-hardness to break the private-key in asymmetric algorithms is a result of its high mathematical complexity. RSA is an asymmetric algorithm that performs successive modular multiplications to encrypt and de-encrypt the information. Therefore, arithmetic operators are the most significant part regarding circuit area and power dissipation. This work evaluates a design space exploration for power- and area-efficient hardware VLSI design in the modular Montgomery multiplier employed in the RSA algorithm.

关键词： Hardware Computer architecture Adders Power dissipation Public key Very large scale integration

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：