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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Morgana M. A. da Rosa Guilherme Paim Leandro M.G. Rocha Eduardo A.C. da Costa Sergio Bampi Graduate Program on Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9781728160443

ISBN: (纸本)9781728160450

This work explores the 8-2 adder compressor in the addition tree of the Sum of Squared Differences (SSD) architecture. SSD is a distortion metric of the motion estimation in the High-Efficiency Video Coding (HEVC) standard. Distortion metrics are the most time-consuming operations of the encoder. SSD hardware architecture consists of a sum tree that accumulates the calculation of the partial values. The addition tree in the SSD opens an opportunity of exploring efficient addition schemes such as the combinations of efficient adder compressors. The SSD architectures herein presented are compared regarding power dissipation using real video sequences. Our work overcomes the state-of-the-art related work which they investigated different SSD hardware architectures concluding that employing the synthesis tool arithmetic operators are the best choice to reduce the power dissipation. According to our results, we reveal that the SSD employing the 8-2 hierarchical adder compressor combined with a Brent-Kung adder in the final sum saves on average 29.4 % of total power dissipation, when comparing with SSD implemented using the arithmetic operators automatically selected by the synthesis tool.

关键词： Compressors Adders Logic gates Computer architecture Tools Measurement Distortion

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Energy-Efficient Haar Transform Architectures Using Efficient Addition Schemes

Energy-Efficient Haar Transform Architectures Using Efficien...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Henrique Seidel Morgana da Rosa Guilherme Paim Eduardo da Costa Sergio Almeida Sergio Bampi Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9781728134277

ISBN: (纸本)9781728134284

This paper proposes an energy-efficient Haar transform architecture using efficient adders circuits. Nine levels of decomposition in a fixed-point format are used in the architectures. The Processing Module (PM) of Haar explores efficient Parallel Prefix Adders (PPA) and adder compressors. Since power-of-two operations approximate one of the inputs of the PM module, efficient adder compressors implement them. It allowed a very high precision adjustment of the transform coefficient. The architectures were described in VHDL and synthesized using the ST 65nm CMOS cell library. The results show that the Haar architecture with 4-2 and 5-2 compressors in the PM module, both with the recombination line with a Sklansky (SK) adder, is more efficient. It has a reduction of 33.6% in the cell area, with a 35.7% reduction in total power in comparison with the literature. Moreover, the Haar architecture with 4-2 and 5-2 adder compressors is more efficient than the one using the tool-selected implementation of the behavioral "+" (sum) in VHDL, with 23% of power reduction.

关键词： Adders Compressors Computer architecture Discrete wavelet transforms Microprocessors

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The Radix-2m Squared Multiplier

The Radix-2m Squared Multiplier

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Morgana M. A. da Rosa Guilherme Paim Leandro M. G. Rocha Eduardo A. C. da Costa Sergio Bampi Graduate Program on Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil Graduate Program on Microelectronics (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9781728160443

ISBN: (纸本)9781728160450

Multipliers are present in a large variety of applications. However, it is usually responsible for most of the power dissipation. On the other hand, the squared multiplier is a particular case of the general-purpose multiplier, in which both operands are the same, proportioning many architecture optimizations. This paper introduces the radix-2 m squared array multiplier architecture. Our architecture proposal for the squared multiplier is the first to reduces the partial products by splitting the operands into mbit groups. Our squared multiplier architecture explores different adder schemes in the multipliers adder tree. As a case study, we demonstrate our squared multiplier proposal for m=2 (radix-4). We investigated the Wallace and Dadda addition trees employing as final carry propagating adder (CPA) the Ripple Carry adder (RCA) and with the adder automatically selected by the synthesis tool. Our best radix-4 squared multiplier proposal employs the Dadda technique and the RCA to implement the adder tree, showing significant energy savings of 20.5%, 56.5%, and 47.4%, for 8, 16, and 32 bits, respectively, compared to the squared multiplier automatically selected by the synthesis tool. Furthermore, our best radix-4 squared multiplier proposal outperforms the Vedic squared multiplier with energy savings in about 21.5%, 71.0%, and 9.0%, respectively, for 8, 16, and 32 bits.

关键词： Adders Tools Proposals Vegetation Computer architecture Optimization Logic gates

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Improving the Partial Product Tree Compression on Signed Radix-2m Parallel Multipliers

Improving the Partial Product Tree Compression on Signed Rad...

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Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)

作者： Leandro M. G. Rocha Morgana Macedo Guilherme Paim Eduardo Costa Sergio Bampi Graduate Program in Microelectronics (PGMicro) - Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil Graduate Program on Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9781728170442

ISBN: (纸本)9781728170459

Arithmetic operations are intrinsic to any embedded devices, and they usually have a significant impact on the circuit speed, area, and power consumption. Applications like video processing, digital signal processing, machine learning, among others, rely heavily on multipliers to execute their algorithms. Radix-2 m multipliers have been reported as one of the most power-efficient circuits. However, their architecture has not been explored nor optimized to improve the circuit quality. This work proposed two sign extension optimization techniques for these multipliers, aiming for better power efficiency and a smaller area. The baseline radix-4 (m=2) multiplier and its optimized versions were synthesized in a commercial 65nm technology to evaluate their performance. Results show that the optimized versions achieve power efficiency gains from 16.4% up to 78.6%, with circuit area reduction up to 49.2%.

关键词： Adders Optimization Power dissipation Computer architecture Digital signal processing Signal processing algorithms Standards

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Topological transformations of a nematic drop

arXiv

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arXiv 2023年

作者： Koizumi, Runa Golovaty, Dmitry Alqarni, Ali Li, Bing-Xiang Sternberg, Peter J. Lavrentovich, Oleg D. Advanced Materials and Liquid Crystal Institute Materials Science Graduate Program Kent State University KentOH44242 United States Department of Mathematics The University of Akron AkronOH44325-4002 United States College of Electronics and Optical Engineering College of Microelectronics Nanjing University of Posts and Telecommunications Nanjing210023 China Department of Mathematics Indiana University BloomingtonIN47405 United States Department of Physics Kent State University KentOH44242 United States

Morphogenesis of living systems involves topological shape transformations which are highly unusual in the inanimate world. Here we demonstrate that a droplet of a nematic liquid crystal changes its equilibrium shape from a simply-connected tactoid, which is topologically equivalent to a sphere, to a torus, which is not simply-connected. The topological shape transformation is caused by the interplay of nematic elastic constants, which facilitates splay and bend of molecular orientations in tactoids but hinders splay in the toroids. The elastic anisotropy mechanism might be helpful in understanding topology transformations in morphogenesis and paves the way to control and transform shapes of droplets of liquid crystals and related soft materials. © 2023, CC BY.

关键词： Drops

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Ξ hypernuclei 15Ξ C12Ξ Be and ΞN two-body interaction

arXiv

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arXiv 2022年

作者： Tanimura, Yusuke Sagawa, Hiroyuki Sun, Tingting Hiyama, Emiko Department of Physics Tohoku University Sendai980-8578 Japan Graduate Program on Physics for the Universe Tohoku University Sendai980-8578 Japan Center for Mathematics and Physics The Univeristy of Aizu Fukushima Aizu-Wakamatsu965-8580 Japan RIKEN Nishina Center Saitama Wako351-0198 Japan School of Physics and Microelectronics Zhengzhou University Zhengzhou450001 China

We study the energy spectra of Ξ hypernuclei 15Ξ C and 12Ξ Be with a relativistic mean field (RMF) model with meson exchange ΞN interactions. The RMF parameters are optimized to reproduce the average energy of KINKA and IRRAWADDY events for the ground state and also the average energy of KISO and IBUKI events for the excited state in 15Ξ C. The potential depth of average ΞN mean field potential is found to be about −12 MeV in the nuclear matter limit. We further introduce the two-body s- and p-wave interactions between valence nucleons and Ξ particle. We found that the s-wave interaction deduced from the HAL LQCD results is rather weak to obtain the energy difference between IRRAWADDY and KINKA events. The p-wave interaction is added and fitted to reproduce the energy difference. The resulting interaction together with the s-wave one gives a reasonable energy simultanously for the IBUKI event as an excited Ξp state. The model is further applied to predict the energy spectrum of 12Ξ Be. © 2022, CC BY.

关键词： Spectroscopy

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Two-transistor voltage-measurement-based test structure for fast extraction of MOS mismatch design parameters 32

Two-transistor voltage-measurement-based test structure for ...

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32nd IEEE International Conference on Microelectronic Test Structures, ICMTS 2019

作者： Brito, Juan Pablo Martinez Bampi, Sergio Graduate Program on Microelectronics - PGMICRO Federal University of Rio Grande Do sul - UFRGS Brazil CEITEC S.A. Semiconductors Porto Alegre Brazil

ISBN: (纸本)9781728114668

This paper proposes a new test structure and a measurement method for measuring MOS transistors mismatches. The structure is based on the combination of two stacked MOS transistors and the measurement methodology relies on two single DC voltage measurements. The method allows to extract separately σ(δ VTH) and σ(Δβ/β) and enables fast extraction of design MOS mismatch parameters such as AVTH and Aβ with less than 2% error. The simple data post-processing algorithm results in an increase of 30x in the measurement speed with data correlation coefficient not less than 0.94 (R2≥0.94). Rapid address decoding and bias configuration have been used in order to select each device in a two-dimensional (2D) DUT matrix of FETs. The experimental data presented herein for analysis is taken from measurements in a prototype fabricated in 65nm CMOS bulk process. © 2019 IEEE.

关键词： Voltage measurement

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Smart photonic wristband for pulse wave monitoring

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Opto-Electronic Science 2024年第12期3卷 12-27页

作者： Renfei Kuang Zhuo Wang Lin Ma Heng Wang Qingming Chen Arnaldo Leal Junior Santosh Kumar Xiaoli Li Carlos Marques Rui Min Center for Cognition and Neuroergonomics State Key Laboratory of Cognitive Neuroscience and LearningBeijing Normal UniversityZhuhai 519087China College of Science Shenyang Aerospace UniversityShenyang 110136China School of Microelectronics Science and Technology Guangdong Provincial Key Laboratory of Optoelectronic Information Processing Chips and SystemsSun Yat-Sen UniversityZhuhai 519082China Graduate Program in Electrical Engineering Federal University of Espírito SantoFernando Ferrari AvenueVitoria 29075-910Brazil Department of Electronics and Communication Engineering Koneru Lakshmaiah Education FoundationVaddeswaramAndhra Pradesh 522302India CICECO-Aveiro Institute of Materials Physics DepartmentUniversity of AveiroAveiro 3810-193Portugal

Real-time acquisition of human pulse signals in daily life is clinically important for cardiovascular disease monitoring and ***,we propose a smart photonic wristband for pulse signal monitoring based on speckle pattern analysis with a polymer optical fiber(POF)integrated into a sports *** different speckle pattern processing algorithms and POFs with different core diameters were *** results indicated that the smart photonic wristband had a high signal-to-noise ratio and low latency,with the measurement error controlled at approximately 3.7%.This optimized pulse signal could be used for further medical diagnosis and was capable of objectively monitoring subtle pulse signal changes,such as the pulse waveform at different positions of Cunkou and pulse waveforms before and after *** the assistance of artificial intelligence(AI),functions such as gesture recognition have been realized through the established prediction model by processing pulse signals,in which the recognition accuracy reaches 95%.Our AI-assisted smart photonic wristband has potential applications for clinical treatment of cardiovascular diseases and home monitoring,paving the way for medical Internet of Things-enabled smart systems.

关键词： smart healthcare specklegram pulse monitoring gesture recognition artificial intelligence wearable sensor

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Approximate SATD Hardware Accelerator Using the 8 × 8 Hadamard Transform

Approximate SATD Hardware Accelerator Using the 8 × 8 Hadam...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Matheus F. Stigger Victor H. S. Lima Leonardo B. Soares Claudio M. Diniz Sergio Bampi Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil Federal Institute of Rio Grande do Sul (IFRS) Rio Grande Brazil Graduate Program in Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9781728134277

ISBN: (纸本)9781728134284

Sum of Absolute Transformed Differences (SATD) is a distortion metric based on the Hadamard Transform. It is used in current video encoders inside the refinement stage of motion estimation, which decides the best block of pixels to be used as prediction for each block to be encoded. To reduce the computational effort incurred by the SATD calculation, this work proposes an approximate SATD hardware accelerator by excluding columns of adders/subtractors of the 8 × 8 Hadamard Transform (HT). The proposed approximate accelerator reduces energy by up to 40.78% compared to the precise SATD accelerator.

关键词： Transforms Computer architecture Hardware Video coding Adders Registers Software

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Performance and Variability Trade-offs of CMOS PTAT Generator Topologies for Voltage Reference Applications

Performance and Variability Trade-offs of CMOS PTAT Generato...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Vanessa F. de Lima Rodrigo Ataide Sergio Bampi Hamilton Klimach Microelectronics Graduate Program UFRGS Porto Alegre RS Brazil Informatics Institute UFRGS Porto Alegre RS Brazil Electrical Engineering Department UFRGS Porto Alegre RS Brazil

ISBN: (数字)9781728196251

ISBN: (纸本)9781728196268

This work presents the analysis, design, and performance evaluation of three usual CMOS proportional to absolute temperature (PTAT) voltage generators, with emphasis on variability effects. Minimization or compensation of the main error sources, such as fabrication variability and intrinsic non-linearities, is an important design challenge required to increase the precision and robustness of a voltage reference. The CMOS PTAT topologies are analytically described and design methodologies for PTAT circuits in subthreshold are presented. The compromises between design conditions and resulting performance are evaluated through simulation for these three PTAT generators, including linearity with temperature, temperature coefficient (TC), and variability impact. Monte-Carlo simulations demonstrated the sensitivity of each topology to fabrication variability, showing that the self-cascode MOSFET structure presents the best accuracy of TC, nominal PTAT voltage, and linearity with temperature.

关键词： Topology Generators MOSFET Temperature sensors Integrated circuit modeling Threshold voltage Semiconductor device modeling

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