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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Brunno A. Abreu Mateus Grellert Sergio Bampi Graduate Program in Microelectronics (PGMICRO) INF-UFRGS Federal University of Rio Grande do Sul Porto Alegre Brazil Department of Informatics and Statistics − INE Federal University of Santa Catarina (UFSC) Florianópolis Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

The use of Machine Learning techniques in battery-powered devices has increased in recent years. Therefore, evaluating power-accuracy trade-offs of inference models has become important. This work explores decision trees architectures, analyzing the effects of model complexity and approximation in power and accuracy. By quantizing the inputs to limited widths, we increased the accuracy of the models in up to 8.7% compared to precise cases. In terms of power, the variation in model complexity was more significant than in input width, as we obtained reductions of up to 97% by decreasing the tree depth, compared to 88% when decreasing the width.

关键词： Complexity theory Hardware Integrated circuit modeling Training Analytical models Decision trees Quantization (signal)

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A comparative study between FinFET and CMOS-based SRAMs under resistive defects 20

A comparative study between FinFET and CMOS-based SRAMs unde...

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20th IEEE Latin American Test Symposium, LATS 2019

作者： Copetti, T.S. Balen, T.R. Brum, E. Aquistapace, C. Poehls, L. Bolzani Graduate Program on Microelectronics-PGMICRO Universidade Federal Do Rio Grande Do sul Porto Alegre Brazil School of Engineering Pontifical Catholic University of Rio Grande Do sul Porto Alegre Brazil

ISBN: (纸本)9781728117560

Due to several factors, such as Process Variations (PV), increased leakage current, Random Dopant Fluctuation (RDF), and mainly the Short-Channel Effect (SCE), the miniaturization of planar CMOS transistors reached its limit at the 22nm node. To continue the miniaturization process via technology down-scaling, while preserving system reliability and performance, FinFET devices arise as an alternative to substitute the CMOS transistors. Additionally, Static Random-Access Memories (SRAMs) have been increasingly occupying a great part of Systems-on-Chips (SoCs) silicon area. Designed to reach densities at the limit of the manufacturing process, make this component susceptible to manufacturing defects, including resistive defects. Such defects can escape traditional manufacturing tests, because they may cause dynamic faults during circuits' lifetime. In this context, a comparison between a 20nm FinFET-based SRAM block and a commercial 65nm CMOS-based SRAM block focusing on resistive defects is carried out. The behavior of defective cells operating over different temperature sets has been investigated by means of SPICE simulations. Results show an expressively higher occurrence of dynamic faults induced by resistive defects in FinFET-based memories when compared to CMOS technology. © 2019 IEEE.

关键词： Defects

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Maximizing the Power-Efficiency of the Approximate Pruned Modified Rounded DCT Exploiting Approximate Adder Compressors

Maximizing the Power-Efficiency of the Approximate Pruned Mo...

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IEEE International New Circuits and Systems Conference

作者： Guilherme Paim Leandro M. G. Rocha Eduardo A. C. da Costa Sergio Bampi Graduate Program in Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Brazil

This paper proposes the use of approximate adder compressors for a low-power 8-point Modified Rounded Discrete Cosine Transform (MRDCT_(10)) implementation. The algebraic approximation of the MRDCT was previously introduced in the literature, whose resultant matrix is only composed of 0, 1 and -1 values. Therefore, the MRDCT can be efficiently implemented using only adders and subtractors. We present an environment for the synthesis of the MRDCT in Cadence Encounter RTL Compiler tool. The synthesis reports are based on a set of real images as input vectors to obtain valid power results. Our results show that the use of approximate adder/subtractor compressors in hardwired state-of-the-art 8-point approximate MRDCT_(10) achieves savings ranging from 26% to 52.54% when compared with the macro function (+) from the tool.

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Exploring Architectural Solutions for an Energy-Efficient Kalman Filter Gain Realization

Exploring Architectural Solutions for an Energy-Efficient Ka...

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Pedro T. L. Pereira Guilherme Paim Patrícia Ücker Eduardo Costa Sérgio Almeida Sergio Bampi Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Brazil Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Brazil

The Kalman filter is a signal processing algorithm that plays an essential role in real-time mobile applications as nano drones navigation, spacecraft orbit control, GPS positioning, image recognition, and sensor data fusion for wearable health monitoring. However, the Kalman filter is a compute-intensive kernel since it implements a high amount of complex matrix operations like multiplications and inversions. The most timing-consuming tasks of the Kalman filter is the Kalman gain. Therefore, this work presents four architectural solutions to explore real-time and energy-efficient Kalman gain processing.

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A 300mV-Supply, 2nW-Power, 80pF-Load CMOS Digital-Based OTA for IoT Interfaces

A 300mV-Supply, 2nW-Power, 80pF-Load CMOS Digital-Based OTA ...

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IEEE International Conference on Electronics, Circuits and Systems

作者： Pedro Toledo Paolo Crovetti Hamilton Klimach Sergio Bampi Graduate Program in Microelectronics (PGMICRO) Federal University of Rio Grande do Sul Politecnico di Torino

This paper presents a power-efficient Ultra Low Voltage (ULV) Digital-Based Operational Transconductance Amplifier (DB-OTA), which uses static logic gates and processes digitally the analog input signal. Post-layout simulations in 180nm CMOS technology show that at 300mV supply voltage the circuit consumes just 2nW while driving a capacitive load of 80pF with Total Harmonic Distortion lower than 5% at 100mV input signal swing. The total silicon area is 1,426 μm~2. The maximum energy efficiency supply for the DB-OTA and its scalability to 40nm CMOS technology node are also demonstrated.

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Flexible Temperature-Pressure Organic Sensor

Flexible Temperature-Pressure Organic Sensor

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microelectronics Technology and Devices (SBMicro)

作者： L.P. Martins H.I. Boudinov Federal University of Rio Grande do Sul: Microelectronics Graduate Program (PPGMicro) Porto Alegre Brazil

Our work intends to develop dual-parameter pressure-temperature sensors by taking advantage of the independent thermoelectric and piezo resistive effects in a single flexible and compressible conductive foam. Such device allows to make measurements of simultaneous temperature and pressure monitoring by transducing external stimuli into separate electrical signals. The devices can be self-powered by a temperature gradient with a promising temperature and pressure detection resolution for applications in artificial intelligence and healthcare systems. Here, we describe the suggested method and discuss preliminary sensor results.

关键词： Temperature sensors Resistance Films Temperature measurement Skin Transistors

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Improved ISFET readout circuit: Characterization and comparison 4

Improved ISFET readout circuit: Characterization and compari...

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4th International Symposium on Instrumentation Systems, Circuits and Transducers, INSCIT 2019

作者： De Castro, Luis Smith Oliveira De Moraes Cruz, Carlos Augusto Cardoso, Valtemar Fernandes Da Silva, Luciano Lourenco F. Pelegrini, Marcus Vinicius Marques, Greicy Costa Graduate Program in Electrical Engineering Department of Electronics and Computation Federal Federal University of Amazonas Manaus AM Brazil Senai Institute of Innovation in Microelectronics Manaus AM Brazil Department of Electronics and Computation Federal University of Amazonas Manaus AM Brazil

ISBN: (纸本)9781728121093

An improved readout circuit topology for Ion Sensitive Field Effect Transistor (ISFET) is presented in this work. The proposed circuit is derived from two circuits presented in the literature: CIMP (Complementary ISFET-MOSFET Pair) with gate feedback and AIS (Active ISFET Sensor) readouts. In order to assert the improvements concerning sensitivity and stability, the proposed circuit behavior is compared against three other related circuits previously presented in the literature. BSIM3v3 and ISFET macromodel SPICE simulations results show that the proposed circuits present improved in sensitivity, linearity and stability when compared with classical circuits. All circuits were simulated using transistors in O.35f.1m CMOS technology. © 2019 IEEE.

关键词： Timing circuits

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Exploring Motion Vector Cost with Partial Distortion Elimination in Sum of Absolute Differences for HEVC Integer Motion Estimation

Exploring Motion Vector Cost with Partial Distortion Elimina...

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IEEE International New Circuits and Systems Conference

作者： Brunno Abreu Mateus Grellert Guilherme Paim Thomas Fontanari Leandro M. G. Rocha Eduardo A. C. da Costa Sergio Bampi Graduate Program in Microelectronics Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil Graduate Program in Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

Integer Motion Estimation (IME) is one of the most costly steps in the video coding process, being responsible for 60% of the total encoding time. Two parameters are considered when calculating the redundancies (distortion) between video blocks: Sum of Absolute Differences (SAD) and motion vector cost (MV_(cost)). Partial Distortion Elimination (PDE) techniques may be used to optimize the calculation of the SAD unit itself, in order to avoid the computation of candidates that will certainly not be selected in the IME. This paper proposes an optimization in the distortion calculation by taking advantage of the PDE technique in SAD operation by including MVcost, in order to save even more cycles when compared to standard PDE usage, considering the High Efficiency Video Coding (HEVC) standard. We found out that the inclusion of MV_(cost) in the distortion cost achieves a quality increase of up to 1.28%. We compare three versions: adding MV_(cost) before/after SAD using a multiplexer, and before SAD with a Carry-Save Adder (CSA). The use of PDE including MV_(cost) before SAD calculation using a multiplexer achieves an average reduction of 17.5% in the energy consumption when compared to accumulating MV_(cost) after SAD. When using the CSA, we obtain an additional average reduction of 1.94%.

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Optomechanical dissipative solitons (vol 600, pg 75, 2021)

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NATURE 2022年第7896期602卷 E24-E24页

作者： Zhang, Jing Peng, Bo Kim, Seunghwi Monifi, Faraz Jiang, Xuefeng Li, Yihang Yu, Peng Liu, Lianqing Liu, Yu-xi Alu, Andrea Yang, Lan Department of Electrical and Systems Engineering Washington University St. Louis MO USA Department of Automation Tsinghua University Beijing P. R. China Photonics Initiative Advanced Science Research Center City University of New York New York NY USA Physics Program Graduate Center City University of New York New York NY USA State Key Laboratory of Robotics Shenyang Institute of Automation Chinese Academy of Sciences Shenyang P. R. China Institute of Microelectronics Tsinghua University Beijing P. R. China

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Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects

Evaluating the Impact of Ionizing Particles on FinFET -based...

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Latin American Test Workshop, LATW

作者： Thiago Copetti Guilherme Cardoso Medeiros Mottaqiallah Taouil Said Hamdioui Letícia Bolzani Poehls Tiago Balen Graduate Program on Microelectronics - PGMICRO Federal University of Rio Grande do Sul Porto Alegre Brazil Computer Engineering Laboratory Delft University of Technology Delft The Netherlands School of Engineering Pontifical Catholic University of Rio Grande do Sul Porto Alegre Brazil

ISBN: (数字)9781728187310

ISBN: (纸本)9781728187327

Fin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. Despite demonstrating improvements on short channel effect and overcoming the growing leakage problem of planar CMOS technology, the continuity of feature size miniaturization allowed by FinFETs tends to increase sensitivity to Single Event Upsets (SEUs) caused by ionizing particles, especially in blocks with higher transistor densities as Static Random-Access Memories (SRAMs). Variation during the manufacturing process has introduced different types of defects that directly affect the SRAM's reliability, such as weak resistive defects. As some of these defects may cause dynamic faults, which require more than one consecutive operation to sensitize the fault at the logic level, traditional test approaches may fail to detect them and test escapes can occur. These undetected faults associated with weak resistive defects may affect the FinFET -based SRAM reliability during the lifetime. In this context, this paper proposes to investigate the impact of ionizing particles on the reliability of FinFET -based SRAMs in the presence of weak resistive defects. Firstly, a TCAD model of a FinFET-based SRAM cell is proposed in order to allow the evaluation of the ionizing particle's impact. Then, SPICE simulations are performed considering the current pulse parameters obtained with TCAD. In this step, weak resistive defects are injected into the FinFET-based SRAM cell. Results show that weak defects may have either a positive or negative influence on the cell reliability against SEUs caused by ionizing particles.

关键词： FinFETs SRAM cells Computational modeling Reliability SPICE Transient analysis

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