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International Symposium on Instrumentation Systems, Circuits and Transducers (INSCIT)

作者： Luís Smith Oliveira de Castro Carlos Augusto de Moraes Cruz Valtemar Fernandes Cardoso Luciano Lourenço F. da Silva Marcus Vinicius Pelegrini Greicy Costa Marques Graduate Program in Electrical Engineering Federal University of Amazonas Manaus AM Brazil Senai Institute of Innovation in Microelectronics Manaus AM Brazil Federal University of Amazonas Manaus Brazil Federal University of Amazonas Manaus AM Brazil

An improved readout circuit topology for Ion Sensitive Field Effect Transistor (ISFET) is presented in this work. The proposed circuit is derived from two circuits presented in the literature: CIMP (Complementary ISFET-MOSFET Pair) with gate feedback and AIS (Active ISFET Sensor) readouts. In order to assert the improvements concerning sensitivity and stability, the proposed circuit behavior is compared against three other related circuits previously presented in the literature. BSIM3v3 and ISFET macromodel SPICE simulations results show that the proposed circuits present improved in sensitivity, linearity and stability when compared with classical circuits. All circuits were simulated using transistors in O.35f.1m CMOS technology.

关键词： Integrated circuit modeling Artificial intelligence Mathematical model Logic gates Semiconductor device modeling MOSFET Sensitivity

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Optical and Atomic Force Microscopy Study of Non-covalently functionalized CVD Graphene

Optical and Atomic Force Microscopy Study of Non-covalently ...

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IEEE International Conference on Nano/Micro Engineered and Molecular Systems

作者： Abayomi Omolewu Guangyi Shi Tian Ryan Xiangbo Meng Uchechukwu Wejinya Microelectronics-Photonics Graduate Program University of Arkansas Fayetteville Arkansas USA Scics Peking University at Wuxi Wuxi China Chemistry and Biochemistry Department University of Arkansas Fayetteville Arkansas USA Department of Mechanical Engineering University of Arkansas Fayetteville Arkansas USA

Chemical functionalization is a method that is being explored to take advantage of the intriguing properties of graphene and its derivatives. Surfactant treatments have been successfully employed to non-covalently functionalize graphitic materials such as carbon nanotube and graphite. However, there is still need to investigate the surfactant treatment approach for commercially available chemical vapor deposited (CVD) graphene on silicon-silicon dioxide substrate. CVD graphene is one of the large-scale graphene available;hence, it is essential to understand how surfactants interact with it. This work presents the optical and atomic force microscopy study of non-covalently-functionalized graphene using Sodium Dodecyl Sulphate. CVD graphene on silicon/silicon dioxide (Si/SiO_2) substrates were treated with different surfactant concentrations for different times. Unlike other derivatives of graphene, like carbon nanotube and graphite where the delamination of graphene sheet from the substrate is not a major concern, results show that the stability of the CVD graphene on the substrate is highly dependent on the concentration of the surfactant used for modifying the surface of the graphene, and the duration of treatment. Higher concentration of surfactant treatment was achieved by dissolving the surfactant with water and isopropyl alcohol. The result also suggests that different concentrations of surfactant affect the surface roughness of the functionalized graphene.

关键词： Graphene Surfactants Substrates Delamination Nanoparticles Zinc oxide

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AFM based Topography Characterization of Smooth, Nanotextured, and Microtextured Surfaces

AFM based Topography Characterization of Smooth, Nanotexture...

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IEEE International Conference on Micro/Nano Sensors for AI, Healthcare, and Robotics

作者： Uchechukwu C. Wejinya Guangyi Shi Abayomi Omolewu Department of Mechanical Engineering University of Arkansas Peking University Shenzhen Graduate School Microelectronics-Photonics Graduate Program University of Arkansas

ISBN: (纸本)9781538694091;9781538694084

Surface topography is important to the function of many kinds of industrial products and is constantly growing with the increase advancement of technology. It is important to understand surface topography measurement and how to control it effectively. Surface roughness is an important parameter of topography characterization and is quantified by the vertical deviations of a real surface from its ideal form. Therefore, depending on the application it may be desirable to have either a rough surface or a very smooth surface. Rough surfaces can be desirable for cell adhesion and plays a great role in biological or biomedical application. Smooth surfaces can be desirable in applications where there are two interacting surfaces and minimal wear between the two is needed. This work addresses the surface topography characterizing of a smooth, nanotextured, and microtextured surface.

关键词： Rough surfaces Surface roughness Surface topography Surface texture Surface treatment Response surface methodology

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Thermodynamic and Thermoelectric properties of CoFeYGe (Y= Ti, Cr) quaternary Heusler alloys: First principle calculations

arXiv

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arXiv 2019年

作者： Haleoot, Raad Hamad, Bothina Microelectronics and Photonics graduate program University of Arkansas FayettevilleAR72701 United States Department of Physics College of Education University of Mustansiriyah Baghdad10052 Iraq Department of Physics University of Arkansas FayettevilleAR72701 United States Physics Department University of Jordan Amman11942 Jordan

Utilizing a material in thermoelectric applications requires a mechanical, thermal, and lattice stability as well a high figure of merit (ZT). In this work, we present the structural, electronic, magnetic, mechanical, thermodynamic, dynamic, and thermoelectric properties of CoFeYGe (Y = Ti, Cr) quaternary Heusler compounds using the density functional theory (DFT). The calculated mechanical properties and phonon dispersions reveal that the structures of these compounds are stable. Both CoFeCrGe and CoFeTiGe compounds show a ferromagnetic and ferrimagnetic half-metallic behavior with band gaps of 0.41 and 0.38 eV, respectively. The lattice thermal conductivity (κL) exhibits low values that reach 3.01 W/(m.K) (3.47 W/(m.K)) for CoFeCrGe (CoFeTiGe) at 1100 K. The optical phonon modes have a large contribution of 60.2% (70.9 %) to κL value for CoFeCrGe (CoFeTiGe). High ZT values of 0.71 and 0.65 were obtained for CoFeCrGe and CoFeTiGe, respectively. Based on our calculations, CoFeCrGe and CoFeTiGe combine both good spintronic and thermoelectric behaviors that may be used in spin injection applications. Copyright © 2019, The Authors. All rights reserved.

关键词： Density functional theory

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Exploiting Partial Distortion Elimination in the Sum of Absolute Differences for Energy-Efficient HEVC Integer Motion Estimation

Exploiting Partial Distortion Elimination in the Sum of Abso...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Brunno Abreu Gustavo Santana Mateus Grellert Guilherme Paim Leandro Rocha Eduardo A. C. da Costa Sergio Bampi Graduate Program in Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil Graduate Program in Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (纸本)9781538674321

Integer Motion Estimation (IME) is an important tool that explores the temporal redundancies in video encoders. It stands out among the most time-consuming and memory intensive tasks in the encoding process. Most of the IME processing is spent on the computation of similarities between pixel blocks, usually using the Sum of Absolute Differences (SAD) as block selection criterion. Designing high-throughput and energy-efficient SAD units is an effective way of increasing the performance of IME architectures. This paper proposes an optimization of SAD units considering the state-of-the-art High Efficiency Video Coding (HEVC) standard, which avoids the computation of candidates that will surely not be selected in the IME search, by applying Partial Distortion Elimination (PDE). The method achieves, without any loss in coding performance, an average reduction of 16.41% and 11.64% in the energy consumption for 1080p and 2160p (4K) videos, respectively, when compared to an HEVC SAD implementation without PDE.

关键词： Encoding Software Motion estimation Computer architecture Video coding Hardware Software algorithms

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A fully integrated CMOS 2.4GHz and 24dBm linear power amplifier 15

A fully integrated CMOS 2.4GHz and 24dBm linear power amplif...

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15th IEEE International New Circuits and Systems Conference, NEWCAS 2017

作者： Guimaraes, Gabriel Teofilo Neves Klimach, Hamilton Duarte Bampi, Sergio Microelectronics Graduate Program Federal University of Rio Grande Do sul Porto Alegre Brazil

ISBN: (纸本)9781509049905

This work presents a fully integrated single-stage 2.4 GHz power amplifier (PA) that was designed in a 180nm CMOS process using a power combining technique to achieve higher output power. A series combining transformer (SCT) combines two cascode differential amplifiers and makes extensive use of virtual AC ground nodes to reduce the impact of bond-wire parasitics. The center-taps of the output transformers are used for 2nd harmonic impedance tuning inside the chip. In post-layout simulation the PA uses a 3.3 V power supply and achieves 24dBm maximum output power at a peak drain efficiency of 23.4%. The test chip returned recently from fabrication and it will undergo electrical tests soon. © 2017 IEEE.

关键词： Power amplifiers

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A 90% efficiency 60 mW MPPT switched capacitor DC - DC converter for photovoltaic energy harvesting aiming for IoT applications 8

A 90% efficiency 60 mW MPPT switched capacitor DC - DC conve...

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8th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2017

作者： Zamparette, Roger Luis Brito Klimach, Hamilton Duarte Bampi, Sergio Microelectronics Graduate Program Federal University of Rio Grande Do sul Porto Alegre RS Brazil

ISBN: (纸本)9781509058594

This work presents a six phase Switched Capacitor (SC) DC - DC converter for photovoltaic Energy Harvesting designed in a 130 nm CMOS process for commercial motes application and Internet of Things (IoT). It tracks the Maximum Power Point (MPP) of a commercial 3 cm × 3 cm 60 mW poly-crystalline photoelectric panel through switching frequency modulation aiming battery recharge. Open-circuit voltage ratio was the chosen Maximum Power Point Tracking (MPPT) strategy. The converter achieves a maximum power conversion efficiency of 90 % for input power higher than 30 mW and is designed to operate with input voltages from 1.25 V to 1.8 V, resulting output voltages from 2.5 V to 3.6 V, respectively. Peripheral circuitry also includes an output over-voltage protection of 3.6 V and the control circuits, that consumes a total of 850 μA at 3.3 V. Complete layout consumes 300 × 700 μm2 of silicon area. The only external components are 6×100 nF capacitors. © 2017 IEEE.

关键词： DC-DC converters

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A Power-Efficient and High-Throughput Hardware Design for 3D-HEVC Disparity Estimation

A Power-Efficient and High-Throughput Hardware Design for 3D...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Murilo Perleberg Vladimir Afonso Ruhan Conceição Altamiro Susin Luciano Agostini Bruno Zatt Marcelo Porto Video Technology Research Group (ViTech) Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

This paper presents a hardware design for the 3D-High Efficiency Video Coding (3D-HEVC) Disparity Estimation (DE) based on the Unidirectional Disparity Search (UDS) algorithm. The architecture was developed to process the four square-shaped Prediction Unit (PU) sizes rather than using all 24 possible PU sizes. These two design approaches caused a coding efficiency degradation of only 0.554% in the BD-rate when compared to the traditional approach whereas allowed a significant reduction in the required calculations and also in the memory accesses, contributing to generate a fast and energy-efficient design. The architecture has a high level of parallelism to reach the desired high throughput and explored clock gating to reduce the power dissipation. As the best of the author's knowledge, this is the first work on literature presenting a hardware design for the 3D-HEVC DE. The architecture was ASIC synthesized and can reach up to 1.457 GHz. This result allows a processing rate of five views of UHD 2160p videos at 52 frames per second. When compared with related works targeting the HEVC Motion Estimation, the developed architecture uses a smaller area, requires a smaller memory, reaches a higher throughput and dissipates at least 92% less power.

关键词： Encoding Hardware Three-dimensional displays Estimation Tools Video sequences Memory management

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Low-Power and High-Throughput Architecture for 3D-HEVC Depth Modeling Mode 4

Low-Power and High-Throughput Architecture for 3D-HEVC Depth...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Mariana Ücker Vladimir Afonso Luan Audibert Altamiro Susin Bruno Zatt Marcelo Porto Luciano Agostini Video Technology Research Group (ViTech) Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (纸本)9781538674321

The 3D-High Efficiency Video Coding (3D-HEVC) is an extension of the High Efficiency Video Coding (HEVC) standard targeting 3D-video encoding. The use of this extension leads to a significant computational-effort increase since new tools are introduced to efficiently encode 3D videos. Therefore, the real-time processing of 3D-videos using 3D-HEVC is highly challenging, and it requires the development of efficient hardware solutions, mainly when mobile devices with energy constraints are considered. This paper focuses on the Depth Modeling Mode 4 (DMM4) encoding mode which is one of the novelties introduced by 3D-HEVC. A low-power and high-throughput architecture was designed and presented in this paper targeting the DMM4, and this architecture was synthesized targeting FPGA and ASIC. The FPGA synthesis was focused on an Altera Stratix V, and the ASIC synthesis was focused on the 45nm Nangate technology. The FPGA and ASIC results showed that the architecture can process UHD 2160p 3D-videos (two views) at 60 fps or to process five views of HD 1080p 3D-videos at 30 frames per second, surpassing the related works in area usage, power dissipation, and processing rate.

关键词： Encoding Tools Calculators Streaming media Computer architecture Field programmable gate arrays Hardware

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A 0.3 V, high-PSRR, picowatt NMOS-only voltage reference using zero-VT active loads 16

A 0.3 V, high-PSRR, picowatt NMOS-only voltage reference usi...

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Proceedings of the 29th Symposium on Integrated Circuits and Systems Design: Chip on the Mountains

作者： David Cordova Arthur C. de Oliveira Pedro Toledo Hamilton Klimach Sergio Bampi Eric Fabris NSCAD Microeletronica and Graduate Program on Microelectronics - UFRGS - Porto Alegre RS Brazil Graduate Program on Microelectronics - UFRGS - Porto Alegre RS Brazil

ISBN: (纸本)9781509027361

A low-voltage high-PSRR CMOS voltage reference operating with picowatt power consumption is presented. The voltage reference is generated from the threshold voltage (VT) difference of two transistors biased in weak inversion. The VT difference is achieved through its dependence with the transistor dimensions. The high-PSRR is obtained using zero-VT transistors as active loads. The final circuit was designed in a 130 nm CMOS process and occupies around 0.0007 mm2 of silicon area while consuming just 18.5 pW at 27°C. Post-layout simulations present a 62 mV reference voltage with a temperature coefficient of 15 ppm/°C, for a temperature range from -25 to 125 °C and a Power Supply Rejection Ratio (PSRR) of -68.7 dB at 0.3 V of supply voltage.

关键词： low-power zero- VT transistor low-voltage voltage reference

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