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检索条件"机构=Graduate Program in Microelectronics - PGMICRO"

共 64 条记录，以下是21-30 订阅

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Combining m=2 Multipliers and Adder Compressors for Power Efficient Radix-4 Butterfly

Combining m=2 Multipliers and Adder Compressors for Power Ef...

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Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Guilherme Ferreira Leandro M. G. Rocha Eduardo Costa Sergio Bampi Graduate Program in Microelectronics (PGMICRO) - Federal University of Rio Grande do Sul (UFRGS) Brazil Graduate Program in Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Brazil

ISBN: (数字)9781728180588

ISBN: (纸本)9781728180595

In this work, we propose a power-efficient hardware architecture for 16-bit m Radix-4 DIT (Decimation in Time) butterfly using radix-2 m multipliers, with m=2, and 4-2 adder compressors. The multiplier uses both Wallace and Dadda schemes in the addition tree, with Carry-Select, Kogge Stone, and '+' operator from the tool internally. We used a method for a realistic power extraction with the standard delay format. The results show that our best-proposed Radix-4 butterfly saves up to 25% of power dissipation when compared with the original Radix-4 butterfly using the synthesis tool operators for both adders and multipliers. The optimized structure combines the m=2 Wallace-based multiplier, employing Kogge-Stone adder into its addition tree, and 4-2 adder compressors.

关键词： Adders Compressors Tools Computer architecture Power dissipation Capacitance Libraries

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An Efficient NLMS-based VLSI Architecture for Robust FECG Extraction and FHR Processing

An Efficient NLMS-based VLSI Architecture for Robust FECG Ex...

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Patrícia U. L. da Costa Guilherme Paim Leandro Rocha Eduardo da Costa Sérgio Almeida Sergio Bampi Graduate Program on Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Brazil Graduate Program on Microelectronics (PGMicro) - Federal University of Rio Grande do Sul (UFRGS) Brazil

ISBN: (数字)9781728160443

ISBN: (纸本)9781728160450

This work presents an efficient NLMS-based VLSI architecture to extract the fetal electrocardiogram (FECG) and detect the fetal heart rate (FHR), using the adaptive filter strategy. The efficient NLMS-based architecture herein investigated can robustly cancel the high-noised mother-related ECG signals, enabling the FHR measurement. We used the Improved Fetal Pan and Tompkins Algorithm (IFPTA) to detect fetal R-peak and calculate the FHR. Our NLMS-based VLSI architecture effectively detects the R-peaks in the extracted FECG with 93.2% accuracy with the only 2.4 mW of total power dissipation.

关键词： Fetal heart rate Very large scale integration Computer architecture Electrocardiography Hardware Thorax Power dissipation

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Exploring Efficient Adder Compressors for Power-Efficient Sum of Squared Differences Design

Exploring Efficient Adder Compressors for Power-Efficient Su...

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Morgana M. A. da Rosa Guilherme Paim Leandro M.G. Rocha Eduardo A.C. da Costa Sergio Bampi Graduate Program on Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9781728160443

ISBN: (纸本)9781728160450

This work explores the 8-2 adder compressor in the addition tree of the Sum of Squared Differences (SSD) architecture. SSD is a distortion metric of the motion estimation in the High-Efficiency Video Coding (HEVC) standard. Distortion metrics are the most time-consuming operations of the encoder. SSD hardware architecture consists of a sum tree that accumulates the calculation of the partial values. The addition tree in the SSD opens an opportunity of exploring efficient addition schemes such as the combinations of efficient adder compressors. The SSD architectures herein presented are compared regarding power dissipation using real video sequences. Our work overcomes the state-of-the-art related work which they investigated different SSD hardware architectures concluding that employing the synthesis tool arithmetic operators are the best choice to reduce the power dissipation. According to our results, we reveal that the SSD employing the 8-2 hierarchical adder compressor combined with a Brent-Kung adder in the final sum saves on average 29.4 % of total power dissipation, when comparing with SSD implemented using the arithmetic operators automatically selected by the synthesis tool.

关键词： Compressors Adders Logic gates Computer architecture Tools Measurement Distortion

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Energy-Efficient Haar Transform Architectures Using Efficient Addition Schemes

Energy-Efficient Haar Transform Architectures Using Efficien...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Henrique Seidel Morgana da Rosa Guilherme Paim Eduardo da Costa Sergio Almeida Sergio Bampi Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9781728134277

ISBN: (纸本)9781728134284

This paper proposes an energy-efficient Haar transform architecture using efficient adders circuits. Nine levels of decomposition in a fixed-point format are used in the architectures. The Processing Module (PM) of Haar explores efficient Parallel Prefix Adders (PPA) and adder compressors. Since power-of-two operations approximate one of the inputs of the PM module, efficient adder compressors implement them. It allowed a very high precision adjustment of the transform coefficient. The architectures were described in VHDL and synthesized using the ST 65nm CMOS cell library. The results show that the Haar architecture with 4-2 and 5-2 compressors in the PM module, both with the recombination line with a Sklansky (SK) adder, is more efficient. It has a reduction of 33.6% in the cell area, with a 35.7% reduction in total power in comparison with the literature. Moreover, the Haar architecture with 4-2 and 5-2 adder compressors is more efficient than the one using the tool-selected implementation of the behavioral "+" (sum) in VHDL, with 23% of power reduction.

关键词： Adders Compressors Computer architecture Discrete wavelet transforms Microprocessors

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Improving the Partial Product Tree Compression on Signed Radix-2m Parallel Multipliers

Improving the Partial Product Tree Compression on Signed Rad...

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Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)

作者： Leandro M. G. Rocha Morgana Macedo Guilherme Paim Eduardo Costa Sergio Bampi Graduate Program in Microelectronics (PGMicro) - Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil Graduate Program on Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9781728170442

ISBN: (纸本)9781728170459

Arithmetic operations are intrinsic to any embedded devices, and they usually have a significant impact on the circuit speed, area, and power consumption. Applications like video processing, digital signal processing, machine learning, among others, rely heavily on multipliers to execute their algorithms. Radix-2 m multipliers have been reported as one of the most power-efficient circuits. However, their architecture has not been explored nor optimized to improve the circuit quality. This work proposed two sign extension optimization techniques for these multipliers, aiming for better power efficiency and a smaller area. The baseline radix-4 (m=2) multiplier and its optimized versions were synthesized in a commercial 65nm technology to evaluate their performance. Results show that the optimized versions achieve power efficiency gains from 16.4% up to 78.6%, with circuit area reduction up to 49.2%.

关键词： Adders Optimization Power dissipation Computer architecture Digital signal processing Signal processing algorithms Standards

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Exploring NLMS and IPNLMS Adaptive Filtering VLSI Hardware Architectures for Robust EEG Signal Artifacts Elimination

Exploring NLMS and IPNLMS Adaptive Filtering VLSI Hardware A...

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Andrei La Rosa Patrícia Ucker Guilherme Paim Eduardo da Costa Sérgio Almeida Sergio Bampi Graduate Program on Computing Federal University of Pelotas (UFPel) Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Brazil Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Brazil

ISBN: (数字)9781728160443

ISBN: (纸本)9781728160450

The elimination of artifacts is a crucial procedure to extract the full potential of the information into the EEG processing. Embedded systems require low circuit area (cost) and efficient hardware architectures. Adaptive filtering plays a vital role as a single method and hybrid approaches for robustly eliminating the noise of the real-world EEG measures. In this paper, we propose and implement hardware architectures for both NLMS and IPNLMS adaptive filters. We investigate the filtering performance and circuit area, timing, and power dissipation of the hardware architecture proposals. To leverage the power-efficiency, we improve our hardware architectures employing the data-gating circuit design technique, which provided up to 20% power savings. Also, applying an HDL-Simulink co-simulation, we perform the hardware architectures tradeoff comparing the synthesis results and filtering performance. Our investigation demonstrates that IPNLMS reduces the time domain error in 11%, increasing less than 1% of circuit area and about the double of the energy per operation, compared to the NLMS.

关键词： Electroencephalography Hardware Computer architecture Convergence Measurement Clocks Proposals

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The Radix-2m Squared Multiplier

The Radix-2m Squared Multiplier

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Morgana M. A. da Rosa Guilherme Paim Leandro M. G. Rocha Eduardo A. C. da Costa Sergio Bampi Graduate Program on Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil Graduate Program on Microelectronics (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9781728160443

ISBN: (纸本)9781728160450

Multipliers are present in a large variety of applications. However, it is usually responsible for most of the power dissipation. On the other hand, the squared multiplier is a particular case of the general-purpose multiplier, in which both operands are the same, proportioning many architecture optimizations. This paper introduces the radix-2 m squared array multiplier architecture. Our architecture proposal for the squared multiplier is the first to reduces the partial products by splitting the operands into mbit groups. Our squared multiplier architecture explores different adder schemes in the multipliers adder tree. As a case study, we demonstrate our squared multiplier proposal for m=2 (radix-4). We investigated the Wallace and Dadda addition trees employing as final carry propagating adder (CPA) the Ripple Carry adder (RCA) and with the adder automatically selected by the synthesis tool. Our best radix-4 squared multiplier proposal employs the Dadda technique and the RCA to implement the adder tree, showing significant energy savings of 20.5%, 56.5%, and 47.4%, for 8, 16, and 32 bits, respectively, compared to the squared multiplier automatically selected by the synthesis tool. Furthermore, our best radix-4 squared multiplier proposal outperforms the Vedic squared multiplier with energy savings in about 21.5%, 71.0%, and 9.0%, respectively, for 8, 16, and 32 bits.

关键词： Adders Tools Proposals Vegetation Computer architecture Optimization Logic gates

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Two-transistor voltage-measurement-based test structure for fast extraction of MOS mismatch design parameters 32

Two-transistor voltage-measurement-based test structure for ...

引用

32nd IEEE International Conference on Microelectronic Test Structures, ICMTS 2019

作者： Brito, Juan Pablo Martinez Bampi, Sergio Graduate Program on Microelectronics - PGMICRO Federal University of Rio Grande Do sul - UFRGS Brazil CEITEC S.A. Semiconductors Porto Alegre Brazil

ISBN: (纸本)9781728114668

This paper proposes a new test structure and a measurement method for measuring MOS transistors mismatches. The structure is based on the combination of two stacked MOS transistors and the measurement methodology relies on two single DC voltage measurements. The method allows to extract separately σ(δ VTH) and σ(Δβ/β) and enables fast extraction of design MOS mismatch parameters such as AVTH and Aβ with less than 2% error. The simple data post-processing algorithm results in an increase of 30x in the measurement speed with data correlation coefficient not less than 0.94 (R2≥0.94). Rapid address decoding and bias configuration have been used in order to select each device in a two-dimensional (2D) DUT matrix of FETs. The experimental data presented herein for analysis is taken from measurements in a prototype fabricated in 65nm CMOS bulk process. © 2019 IEEE.

关键词： Voltage measurement

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Optimizing the Montgomery Modular Multiplier for a Power- and Area-Efficient Hardware Architecture

Optimizing the Montgomery Modular Multiplier for a Power- an...

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Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Mateus Terribele Leme Guilherme Paim Leandro M. G Rocha Patricia Ücker Vitor G. Lima Rafael Soares Eduardo A. C. da Costa Sergio Bampi Graduate Program in Microelectronics (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Graduate Program on Computer Science (PPGC) Federal University of Pelotas (UFPel)

ISBN: (数字)9781728180588

ISBN: (纸本)9781728180595

Cryptography hardware design is a key challenge towards the confidentiality advance in the prominent field of the internet of things (IoT). The rise of IoT embedded devices boosts the demand for power- and area- efficient solutions for cryptography hardware. The higher the robustness of the cryptography algorithm is, the higher are the hardware complexity, the circuit area, and energy consumption. Asymmetric algorithms are a particular class widely employed in ultra-secure cryptosystems. The high time-hardness to break the private-key in asymmetric algorithms is a result of its high mathematical complexity. RSA is an asymmetric algorithm that performs successive modular multiplications to encrypt and de-encrypt the information. Therefore, arithmetic operators are the most significant part regarding circuit area and power dissipation. This work evaluates a design space exploration for power- and area-efficient hardware VLSI design in the modular Montgomery multiplier employed in the RSA algorithm.

关键词： Hardware Computer architecture Adders Power dissipation Public key Very large scale integration

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Approximate SATD Hardware Accelerator Using the 8 × 8 Hadamard Transform

Approximate SATD Hardware Accelerator Using the 8 × 8 Hadam...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Matheus F. Stigger Victor H. S. Lima Leonardo B. Soares Claudio M. Diniz Sergio Bampi Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil Federal Institute of Rio Grande do Sul (IFRS) Rio Grande Brazil Graduate Program in Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9781728134277

ISBN: (纸本)9781728134284

Sum of Absolute Transformed Differences (SATD) is a distortion metric based on the Hadamard Transform. It is used in current video encoders inside the refinement stage of motion estimation, which decides the best block of pixels to be used as prediction for each block to be encoded. To reduce the computational effort incurred by the SATD calculation, this work proposes an approximate SATD hardware accelerator by excluding columns of adders/subtractors of the 8 × 8 Hadamard Transform (HT). The proposed approximate accelerator reduces energy by up to 40.78% compared to the precise SATD accelerator.

关键词： Transforms Computer architecture Hardware Video coding Adders Registers Software

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