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25th IASTED International Conference on Modelling, Identification, and Control, MIC 2006

作者： Das, Sunil R. Biswas, Dhruv Petriu, Emil M. Assaf, Mansour H. Sahinoglu, Mehmet School of Information Technology and Engineering Faculty of Engineering University of Ottawa Ottawa ON K1N 6N5 Canada Department of Computer and Information Science Troy University Montgomery AL 36103 United States

ISBN: (纸本)0889865515

The evolution of the embedded cores-based design paradigm in recent times has created numerous challenging problems for the test design community. To develop suitable test environment and appropriate test methodologies for digital cores-based system-on-chip (SOC) is a fascinating area of research today. This paper attempts to develop viable solution options to these problems based on cores constructed from ISCAS 85 combinational and ISCAS 89 sequential benchmark circuits. The wrapper that separates the core under test from other cores is assumed to be IEEE P1500-compliant. The cores and test access mechanism (TAM) are described in the paper using Verilog HDL, while TAM is implemented as a plain signal transport medium, being shared by all the cores in the SOC. The fault injection is done by a simulator that also generates the tests for the core. The fault simulation process is carried out after successful compilation of the cores, the individual core selection being done by the program running in the background.

关键词： System-on-chip

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Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters

Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain...

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IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

作者： Gang Zeng Youhua Shi Toshinori Takabatake Masao Yanagisawa Hideo Ito Graduate School of Information Science University of Nagoya Japan Department of Computer Science Waseda University Japan Department of Information Science Shonan Institute of Technology Japan Faculty of Engineering Chiba University Japan

ISBN: (纸本)9780769527062;076952706X

A fixing-shifting encoding (FSE) method is proposed to reduce test cost of IP cores. The FSE method reduces test cost by supporting multiple-mode loading test data, i.e., parallel loading, left-direction, and right-direction serial loading for each test slice data. Furthermore, the FSE that utilizes only two test channels can support a large number of internal scan chains and achieve further reduction in test cost by combining with scan chain clustering method. As a non-intrusive and automatic test pattern generation (ATPG) independent solution, the approach is applicable to IP core testing because it requires neither redesign of the core under test (CUT) nor running any additional ATPG for the encoding procedure. In addition, the decoder has low hardware overhead, and its design is independent of the CUT. Experimental results for some large ISCAS 89 benchmarks and an industry ASIC design have proven the efficiency of the proposed approach

关键词： Costs Automatic test pattern generation Circuit testing Automatic testing Decoding System-on-a-chip Hardware Design for testability Feedback information science

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Analysis of PVT composite structure images using a Search Through algorithm

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WSEAS Transactions on Systems 2006年第11期5卷 2708-2712页

作者： Shilbayeh, Nidal F. Iskandarani, Mahmoud Z. Faculty of Computer Science and Information Technology The University of Graduate Studies P.O.BOX 42 11610 Amman Jordan Faculty of Science and Information Technology Al-Zaytoonah Private University of Jordan P.O.BOX 911597 11191 Amman Jordan

An effective NDT (Non-Destructive Testing) image analysis technique for detecting materials damage and defects existence has been developed successfully and applied to PVT images of composite structures. The developed technique is based on converting an image to its equivalent pixel values and then applying Search Through (ST) algorithm to the converted image such that the presence of damage in the composite structure and its extent can be easily verified. The technique has a novel approach to data analysis by employing intensity, RGB signal re-mix. and wavelength variation of a thermally generated IR-beam onto the specimen under test which can be sensed and displayed on a computer screen as an image. Specimen inspection and data analysis are carried out through pixel level re-ordering and shelving techniques within a transformed image file using a sequence grouping and regrouping software system, which is specifically developed for this work.

关键词： Composite structures

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Studies on Estimation of the Sources Number in Blind Source Separation Problems

Studies on Estimation of the Sources Number in Blind Source ...

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SICE Annual Conference

作者： Takaaki Ishibashi Katsuhiro Inoue Hiromu Gotanda Kousuke Kumamaru Graduate School of Computer Science and Systems Engineering Kyushu Institute of Technology Fukuoka Japan Faculty of Computer Science and Systems Engineering Kyushu Institute of Technology Fukuoka Japan Faculty of Humanity-Oriented Science and Engineering Kinki University Fukuoka Japan

ICA (Independent Component Analysis) can separate unknown source signals from their mixture signals without information on the transfer functions, provided that the sources are statistically independent. When the number of the source signals is equal to that of the observed signals, the original sources can be recovered except for indeterminacy of scale and permutation. However, the number of the sources is unknown in a real environment. In this paper, we propose an estimation method for the number of the sources based on the joint distribution of the observed signals under two-sensor configuration. From several simulation results, it is found that the number of the sources is coincident to that of peaks in the histogram of the distribution

关键词： Blind source separation Independent component analysis Speech recognition Acoustic noise Frequency Transfer functions Working environment noise computer science Systems engineering and theory Histograms

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Exploiting loop-level parallelism in the AES algorithm

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WSEAS Transactions on computers 2006年第1期5卷 125-132页

作者： Bielecki, Wlodzimierz Burak, Dariusz Faculty of Computer Science and Information Systems Szczecin University of Technology 49 Zolnierska St. PL-71210 Szczecin Poland

In this paper we present the parallelization process of the AES algorithm (Rijndael) based on loop-level parallelism along with the description of exploited parallelization tools. The data dependence analysis of the most time-consuming loops and appropriate loop transformations were applied in order to parallelize the sequential algorithm. The OpenMP standard was chosen for representing the parallelism of the AES algorithm. Speed-up measurements for a parallel program are presented. A strategy of the parallelization process of the standard modes of operation for the AES algorithm is also described.

关键词： Cryptography

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TCML - an XML-based test case format

TCML - an XML-based test case format

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International Conference on Computing & Informatics (ICOCI)

作者： Mohd Farid Jaafar Mohd Hasan Selamat Abdul Azim Abdul Ghani Faculty of Computer Science and Information Technology Universiti Putra Malaysia Serdang Selangor Darul Ehsan Malaysia

Testing is important and gives the confident to the developer and user; but it is expensive and may consume at least 50% of the total costs involved in developing software. This cost is just for a normal application but if it involves extreme and critical software, the number might increases. As we know, designing test suite for testing is a tedious and meticulous work. We need to have a deep understanding of the program before we could design a good test suite and even an expert tends to miss some test cases. Manual testing for large-scale program is very expensive and frustrating for humans. The same scenario applies in visual programming language (VPL). Visual programming (VP) is a much complex program than conventional one. Testing VP program give users the confidence on what they visualize is correctly transformed according to their perception. Most studies in designing test suites are using requirement specification, complex technique (i.e. Z) and third-party tools that require novices and non-expert user to supply information that is not familiar to them. It is certain that the information they supplied is more or less inaccurate and thus affects the test suite produced. Furthermore, there are no standard structures in exchanging the data about a program. The objective of this paper is to propose an XML-based test case language called test case markup language (TCML).

关键词： XML Software testing Costs Application software HTML computer science information technology Large-scale systems Humans computer languages

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New approach to complexity reduction of intra prediction in advanced multimedia compression

New approach to complexity reduction of intra prediction in ...

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ICCSA 2006: International Conference on Computational science and Its Applications

作者： Yu, Mei Jiang, Gangyi Li, Shiping Li, Fucui Choi, Tae-Young Faculty of Information Science and Engineering Ningbo University Ningbo 315211 China State Key Lab. for Novel Software Technology Nanjing University Nanjing 210093 China Institute of Computer Technology Graduate School Chinese Academy of Sciences Beijing 100871 China Division of Electronics Engineering Ajou University Suwon 442-749 Korea Republic of

ISBN: (纸本)354034070X

H.264 is the new multimedia compression standard developed by VCEG and MPEG. In order to maximize the compression performance, H.264 adopts RDO mode decision techniques at the cost of very remarkable computational complexity. To reduce encoder complexity associated with the intra-prediction mode selection, in this paper, a fast intra prediction mode selection scheme is proposed. It is based on three improvement parts, including improvement of the intra prediction algorithm structure, fast selection between intra 4×4 block mode and intra 16×16 block mode, and the fast 4×4 luma block mode selection based on the luma similarity between reference pixels. Experimental results show that the proposed scheme outperforms Pan's method, and compared with the test model JM8.6 provided by JVT, the proposed scheme reduces 83.10% coding time for intra frames and 50.94% coding time for all the frames while maintaining the PSNR and bit rate. © Springer-Verlag Berlin Heidelberg 2006.

关键词： Large scale systems

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A concurrency control method for parallel btree structures 22

A concurrency control method for parallel btree structures

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22nd International Conference on Data Engineering Workshops, ICDEW 2006

作者： Yoshihara, Tomohiro Kobayashi, Dai Taguchi, Ryo Yokota, Haruo Department of Computer Science Tokyo Institute of Technology Graduate School of Information Science and Engineering 2-12-1 Ookayama Meguro-ku Tokyo152-8552 Japan Science and Technical Research Laboratories Japan Broadcasting Corporation 1-10-11 Kinuta Setagaya-ku Tokyo157-8510 Japan Global Scientific Information and Computing Center Tokyo Institute of Technology 2-12-1 Ookayama Meguro-ku Tokyo152-8550 Japan

ISBN: (纸本)0769525717

A new concurrency control protocol for parallel Btree structures, MARK-OPT, is proposed. MARK-OPT marks the lowest structure-modification-operation (SMO) occurrence point during optimistic latch coupling operations, to reduce the cost of SMO compared to the conventional protocols such as ARIES/IM and INC-OPT. The marking reduces the frequency of restarts for spreading the range of X latches, which will clearly improves the system throughput. Moreover, the MARK-OPT is deadlock free and satisfies the physical consistency requirement for Btrees. These indicate that the MARK-OPT is right and suitable as a concurrency control protocol for Btree structures. This paper also proposes three variations of the protocol, INC-MARKOPT, 2P-INT-MARK-OPT and 2P-REP-MARK-OPT, by focusing on tree structure changes from other transactions. We implement the proposed protocols, the INC-OPT, and the ARIES/IM for the Fat-Btree, a form of parallel Btree, and compare the performance of these protocols using a large-scale blade system. The experimental results indicate that the proposed protocols always improve the system throughput, and the 2P-REP-MARK-OPT is the most useful protocol in a high update environment. Moreover, in the experiment, the low frequency of restarts in the proposed protocols indicates that the marking in the proposed protocols is effective. © 2006 IEEE.

关键词： Concurrency control

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Directed Evolutionary programming: Towards an Improved Performance of Evolutionary programming

Directed Evolutionary Programming: Towards an Improved Perfo...

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Congress on Evolutionary Computation

作者： A.-R. Hedar M. Fukushima Department of Computer Science Faculty of Computer and Information Sciences Assiut University Egypt Department of Applied Mathematics and Physics Graduate School of Informatics Kyoto University Kyoto Japan

Evolutionary programming (EP) is one of the main classes of evolutionary algorithms (EAs). Improving existing EAs is necessary in order to achieve better results and overcome their costly computational complexity. In this paper, we present a new version of EP called Directed Evolutionary programming (DEP) in which more directing strategies with learned termination criteria are invoked to overcome some drawbacks of EP. In DEP, the mutated children are given the chance to improve themselves with the guidance of their parents. The search process in DEP is supported by diversification and intensification schemes in order to keep the diversity, achieve faster convergence and equip the search with an automatic termination criteria. The computational experiments show that DEP is efficient and cheaper than some well-known versions of EP.

关键词： Genetic programming Convergence Evolutionary computation Search methods Mathematics Physics Informatics computer science Computational complexity Computational intelligence

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An efficient schema-based technique for querying XML data

An efficient schema-based technique for querying XML data

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作者： Kha, Dao Dinh Yoshikawa, Masatoshi IMI Project of COE Program Nagoya University Nagoya-shi 464-8601 Japan Graduate School of Information Science Nagoya University Nagoya-shi 464-8601 Japan Directorate for IT Applications Promotion Ministry of Posts and Telematics 18 Nguyen Du Ha noi Viet Nam Directorate for IT Applications Promotion Ministry of Posts and Telematics of Vietnam Viet Nam Graduate School of Information Science Nagoya University Japan ACM Japan IEEE Computer Society Japan IPSJ Japan

As data integration over the Web has become an increasing demand, there is a growing desire to use XML as a standard format for data exchange. For sharing their grammars efficiently, most of the XML documents in use are associated with a document structure description, such as DTD or XML schema. However, the document structure information is not utilized efficiently in previously proposed techniques of XML query processing. In this paper, we present a novel technique that reduces the disk I/O complexity of XML query processing. We design a schema-based numbering scheme called SPAR that incorporates both structure information and tag names extracted from DTD or XML schema. Based on SPAR, we develop a mechanism called VirtualJoin that significantly reduces disk I/O workload for processing XML queries. As shown by experiments. VirtualJoin outperforms many prior techniques. Copyright © 2006 The Institute of Electronics, information and Communication Engineers.

关键词： XML

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