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Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)

作者： Leandro M. G. Rocha Morgana Macedo Guilherme Paim Eduardo Costa Sergio Bampi Graduate Program in Microelectronics (PGMicro) - Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil Graduate Program on Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9781728170442

ISBN: (纸本)9781728170459

Arithmetic operations are intrinsic to any embedded devices, and they usually have a significant impact on the circuit speed, area, and power consumption. Applications like video processing, digital signal processing, machine learning, among others, rely heavily on multipliers to execute their algorithms. Radix-2 m multipliers have been reported as one of the most power-efficient circuits. However, their architecture has not been explored nor optimized to improve the circuit quality. This work proposed two sign extension optimization techniques for these multipliers, aiming for better power efficiency and a smaller area. The baseline radix-4 (m=2) multiplier and its optimized versions were synthesized in a commercial 65nm technology to evaluate their performance. Results show that the optimized versions achieve power efficiency gains from 16.4% up to 78.6%, with circuit area reduction up to 49.2%.

关键词： Adders Optimization Power dissipation Computer architecture Digital signal processing Signal processing algorithms Standards

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Machine Learning Approach to Predicting Tunnel Field-Effect Transistors

Machine Learning Approach to Predicting Tunnel Field-Effect ...

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International Symposium on VLSI Technology, Systems and Applications

作者： Chandni Akbar Narasimhulu Thoti Yiming Li Paralllel and Scientific Computing Laboratory National Yang Ming Chiao Tung University Hsinchu Taiwan EECS International Graduate Program National Yang Ming Chiao Tung University Hsinchu Taiwan Paralllel and Scientific Computing Laboratory EECS International Graduate Program Institue of Communications Engineering National Yang Ming Chiao Tung University Hsinchu Taiwan National Yang Ming Chiao Tung University Hsinchu Taiwan Institue of Communications Engineering National Chiao Tung University Hsinchu Taiwan

We for the first time investigate the possibility to replace the device simulation for tunnel field-effect transistors (TFETs) with a machine learning (ML) algorithm. By incorporating the experimentally validated device simulation, a keyML technique named random forest regression (RFR) model is advanced and applied to predict characteristics of TFETs. The results of this work may benefit the design and fabrication of TFETs based on the well-trained RFR model. Very fast and accurate drain current (ID) prediction in terms of the engineering acceptable root-mean-square (RMSE) error inaugurates TFET technology with ML with a potential application to significantly reduce the computational cost.

关键词： Training TFETs Machine learning algorithms Computational modeling Vegetation Predictive models Data models

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Energy-Efficient Haar Transform Architectures Using Efficient Addition Schemes

Energy-Efficient Haar Transform Architectures Using Efficien...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Henrique Seidel Morgana da Rosa Guilherme Paim Eduardo da Costa Sergio Almeida Sergio Bampi Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9781728134277

ISBN: (纸本)9781728134284

This paper proposes an energy-efficient Haar transform architecture using efficient adders circuits. Nine levels of decomposition in a fixed-point format are used in the architectures. The Processing Module (PM) of Haar explores efficient Parallel Prefix Adders (PPA) and adder compressors. Since power-of-two operations approximate one of the inputs of the PM module, efficient adder compressors implement them. It allowed a very high precision adjustment of the transform coefficient. The architectures were described in VHDL and synthesized using the ST 65nm CMOS cell library. The results show that the Haar architecture with 4-2 and 5-2 compressors in the PM module, both with the recombination line with a Sklansky (SK) adder, is more efficient. It has a reduction of 33.6% in the cell area, with a 35.7% reduction in total power in comparison with the literature. Moreover, the Haar architecture with 4-2 and 5-2 adder compressors is more efficient than the one using the tool-selected implementation of the behavioral "+" (sum) in VHDL, with 23% of power reduction.

关键词： Adders Compressors Computer architecture Discrete wavelet transforms Microprocessors

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The Radix-2m Squared Multiplier

The Radix-2m Squared Multiplier

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Morgana M. A. da Rosa Guilherme Paim Leandro M. G. Rocha Eduardo A. C. da Costa Sergio Bampi Graduate Program on Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil Graduate Program on Microelectronics (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9781728160443

ISBN: (纸本)9781728160450

Multipliers are present in a large variety of applications. However, it is usually responsible for most of the power dissipation. On the other hand, the squared multiplier is a particular case of the general-purpose multiplier, in which both operands are the same, proportioning many architecture optimizations. This paper introduces the radix-2 m squared array multiplier architecture. Our architecture proposal for the squared multiplier is the first to reduces the partial products by splitting the operands into mbit groups. Our squared multiplier architecture explores different adder schemes in the multipliers adder tree. As a case study, we demonstrate our squared multiplier proposal for m=2 (radix-4). We investigated the Wallace and Dadda addition trees employing as final carry propagating adder (CPA) the Ripple Carry adder (RCA) and with the adder automatically selected by the synthesis tool. Our best radix-4 squared multiplier proposal employs the Dadda technique and the RCA to implement the adder tree, showing significant energy savings of 20.5%, 56.5%, and 47.4%, for 8, 16, and 32 bits, respectively, compared to the squared multiplier automatically selected by the synthesis tool. Furthermore, our best radix-4 squared multiplier proposal outperforms the Vedic squared multiplier with energy savings in about 21.5%, 71.0%, and 9.0%, respectively, for 8, 16, and 32 bits.

关键词： Adders Tools Proposals Vegetation Computer architecture Optimization Logic gates

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Exploring Efficient Adder Compressors for Power-Efficient Sum of Squared Differences Design

Exploring Efficient Adder Compressors for Power-Efficient Su...

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Morgana M. A. da Rosa Guilherme Paim Leandro M.G. Rocha Eduardo A.C. da Costa Sergio Bampi Graduate Program on Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9781728160443

ISBN: (纸本)9781728160450

This work explores the 8-2 adder compressor in the addition tree of the Sum of Squared Differences (SSD) architecture. SSD is a distortion metric of the motion estimation in the High-Efficiency Video Coding (HEVC) standard. Distortion metrics are the most time-consuming operations of the encoder. SSD hardware architecture consists of a sum tree that accumulates the calculation of the partial values. The addition tree in the SSD opens an opportunity of exploring efficient addition schemes such as the combinations of efficient adder compressors. The SSD architectures herein presented are compared regarding power dissipation using real video sequences. Our work overcomes the state-of-the-art related work which they investigated different SSD hardware architectures concluding that employing the synthesis tool arithmetic operators are the best choice to reduce the power dissipation. According to our results, we reveal that the SSD employing the 8-2 hierarchical adder compressor combined with a Brent-Kung adder in the final sum saves on average 29.4 % of total power dissipation, when comparing with SSD implemented using the arithmetic operators automatically selected by the synthesis tool.

关键词： Compressors Adders Logic gates Computer architecture Tools Measurement Distortion

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Opportunities and Challenges from Using Animal Videos in Reinforcement Learning for Navigation

arXiv

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arXiv 2022年

作者： Giammarino, Vittorio Queeney, James Carstensen, Lucas C. Hasselmo, Michael E. Paschalidis, Ioannis Ch. Division of Systems Engineering Boston University BostonMA02215 United States Center for Systems Neuroscience Department of Psychological and Brain Sciences Graduate Program for Neuroscience Boston University BostonMA02215 United States College of Engineering Hariri Institute for Computing & Computational Science & Engineering Boston University BostonMA02215 United States

We investigate the use of animal videos (observations) to improve Reinforcement Learning (RL) efficiency and performance in navigation tasks with sparse rewards. Motivated by theoretical considerations, we make use of weighted policy optimization for off-policy RL and describe the main challenges when learning from animal videos. We propose solutions and test our ideas on a series of 2D navigation tasks. We show how our methods can leverage animal videos to improve performance over RL algorithms that do not leverage such observations. © 2022, CC BY.

关键词： Reinforcement learning

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FAME: A Lightweight Spatio-Temporal Network for Model Attribution of Face-Swap Deepfakes

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Expert Systems with Applications 2025年

作者： Wasim Ahmad Yan-Tsung Peng Yuan-Hao Chang Institute of Information Science Academia Sinica Taipei 115 Taiwan Social Networks and Human-Centred Computing Taiwan International Graduate Program Taipei 115 Taiwan Department of Computer Science National Chengchi University Taipei 116 Taiwan

The widespread emergence of face-swap Deepfake videos poses growing risks to digital security, privacy, and media integrity, necessitating effective forensic tools for identifying the source of such manipulations. Although most prior research has focused primarily on binary Deepfake detection, the task of model attribution determining which generative model produced a given Deepfake remains underexplored. In this paper, we introduce FAME (Fake Attribution via Multilevel Embeddings), a lightweight and efficient spatio-temporal framework designed to capture subtle generative artifacts specific to different face-swap models. FAME integrates spatial and temporal attention mechanisms to improve attribution accuracy while remaining computationally efficient. We evaluate our model on three challenging and diverse datasets, which include Deepfake Detection and Manipulation (DFDM), FaceForensics++ (FF++), and FakeAVCeleb (FAVCeleb). The evaluation results show that FAME consistently performs better than existing methods in both accuracy and runtime, highlighting its potential for deployment in real-world forensic and information security applications. The code and pretrained models will be made publicly available at: https://***/wasim004/FAME/ .

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Photocontrol of selective light reflection by oblique helicoidal cholesteric 25

Photocontrol of selective light reflection by oblique helico...

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Liquid Crystals XXV 2021

作者： Thapa, Kamal Iadlovska, Olena S. Bisoyi, Hari Krishna Paterson, Daniel A. Storey, John M.D. Imrie, Corrie T. Li, Quan Shiyanovskii, Sergij V. Lavrentovich, Oleg D. Advanced Materials and Liquid Crystal Institute Kent State University KentOH44242 United States Dept. of Physics Kent State University KentOH44242 United States Department of Chemistry School of Natural and Computing Sciences University of Aberdeen AB24 3UE United Kingdom Materials Science Graduate Program Kent State University KentOH44242 United States

ISBN: (数字)9781510644533

ISBN: (纸本)9781510644526

An oblique helicoidal cholesteric ChOH represents a unique optical material with a pitch that can be tuned by an electric or magnetic field in a broad range from sub micrometers to micrometers. In this work, we demonstrate that the oblique helicoidal cholesteric doped with azoxybenzene molecules and stabilized by an electric field could also be tuned by light irradiation. At a fixed voltage, UV irradiation causes a redshift of the reflection peak by more than 200 nm. The demonstrated effect has the potential for applications such as smart windows, sensors, tunable lasers, and filters. © 2021 SPIE.

关键词： Electric fields

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Artificial Neural Network Model for Steel Strip Tandem Cold Mill Power Prediction 3rd

Artificial Neural Network Model for Steel Strip Tandem Cold ...

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3rd International Conference on Applied Informatics, ICAI 2020

作者： de Oliveira, Danilo G. da Silva, Eliton M. Miranda, Fabiano J. F. Filho, José F. S. Parpinelli, Rafael S. Graduate Program in Applied Computing Santa Catarina State University – UDESC Joinville Brazil Department of Computer Science Santa Catarina State University – UDESC Joinville Brazil ArcelorMittal – Global Research and Development Group São Francisco do Sul Brazil

ISBN: (纸本)9783030617011

In the cold rolling of flat steel strips, electric energy consumption is one of the highest expenses. Predicting the power requirements according to the line and product conditions can significantly impact the energy cost and, thus, on the business’s profitability. This paper proposes predicting the power requirements of a tandem cold rolling mill of steel strips on a coil-to-coil base applying Artificial Neural Networks (ANN) as a uni-variate regression problem. The tests yielded an MSE of 300.39 kW or 2.4% and are better than the acceptable 5% error margin for this project, indicating that the ANN presented satisfactory results. The application of six full-month worth of data in the trained ANN model showed the excellent correlation of the ANN predictions with the measured data, leading to the conclusion that the system is ready for the deployment for daily use for line engineers. Overall, the results obtained show that the steel industry can highly benefit from Industry 4.0 and Artificial Intelligence technologies. © 2020, Springer Nature Switzerland AG.

关键词： Automotive industry

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Scaling Limitations of Line TFETs at Sub-8-nm Technology Node

Scaling Limitations of Line TFETs at Sub-8-nm Technology Nod...

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2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

作者： Thoti, Narasimhulu Li, Yiming Kola, Sekhar Reddy Parallel and Scientific Computing Laboratory Eecs International Graduate Program Institute of Communications Engineering Department of Electrical and Computer Engineering Center for MmWave Smart Radar System and Technologies National Chiao Tung University 1001 Ta-Hsueh Rd Hsinchu300 Taiwan

ISBN: (纸本)9781728142326

The scope of the work is to investigate limitations in device scaling by identifying various parameters of short channel effects (SCEs) in current challenging geometries of the line tunnel field effect transistors (TFETs). Key factors of the considered device, such as the doping and the thickness (tn) of n-epitaxial region, and source-to-drain length (LSDeff) scaling cannot be tuned anymore to boost the device characteristics for the sub-8-nm technology node. The main results of this study indicates that the engineering acceptable performance are achieved at a low doping of 5 1018 cm-3, an optimal tn as low (about 0.5 nm), and a LSDeff greater than 12.5 nm. Hence, the line TFETs below sub-8-nm faces serious bottleneck of scaling and cannot be further scaled with the conventional scaling rule at all. © 2020 IEEE.

关键词： Tunnel field effect transistors

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