This work proposes an ultra-low-energy ECG data compression with VLSI DHWT-based (discrete Haar wavelet transform) architecture to enable storage and transmission in resource-constrained environments. We present origi...
详细信息
Addition units are present across many computational kernels inherent in various error-tolerant applications, including machine learning, signal, image, and video processing. Notably, adder compressors are the target ...
详细信息
This work proposes an accuracy-driven evaluation model of an approximate adder (AxA) called an approximate parallel prefix adder (AxPPA). It explores the significance of approximate computing (AxC) in optimizing perfo...
详细信息
This work presents an optimized exponential function VLSI hardware design by Taylor series expansion. The proposed architecture implements the exponential by approximating the logic design of a 4th-order Taylor series...
详细信息
We present an energy-efficient implementation of the level-2 Pruned Discrete Haar Wavelet Transform (PDHWT-2) for R-peak detection in ECG signals. Approximate computing techniques were employed, including five well-es...
详细信息
Approximate computing (AxC) has emerged as a viable alternative to enhance computational efficiency by leveraging the intrinsic error resilience of many applications. One of the leading strategies of AxC involves expl...
详细信息
We present an energy-efficient implementation of the level-2 Pruned Discrete Haar Wavelet Transform (PDHWT-2) for R-peak detection in ECG signals. Approximate computing techniques were employed, including five well-es...
详细信息
ISBN:
(数字)9798331522124
ISBN:
(纸本)9798331522131
We present an energy-efficient implementation of the level-2 Pruned Discrete Haar Wavelet Transform (PDHWT-2) for R-peak detection in ECG signals. Approximate computing techniques were employed, including five well-established approximate adders (AxPPA, COPY, ETA-I, LOA, and Trunc) and bit truncation (T), to reduce energy consumption while maintaining accuracy above 99% for reliable R-peak detection. By focusing on the second-level detail coefficient $(D_{2})$ for peak detection and pruning the approximation coefficient, the PDHWT-2 design achieves significant reductions in computational complexity. The architecture, evaluated with ECG signals from the MIT-BIH database, maintained accuracy above 99% even with aggressive bit truncation and approximation, ensuring reliable medical-grade analysis. Integration of approximate adders (AxAs) and truncation enabled significant power and area savings. Specifically, the use of the AxPPA demonstrated power savings of up to 40% with area reductions of around 45%, making the PDHWT-2 a highly efficient solution for low-power ECG monitoring systems.
Approximate computing (AxC) has emerged as a viable alternative to enhance computational efficiency by leveraging the intrinsic error resilience of many applications. One of the leading strategies of AxC involves expl...
详细信息
ISBN:
(数字)9798331522124
ISBN:
(纸本)9798331522131
Approximate computing (AxC) has emerged as a viable alternative to enhance computational efficiency by leveraging the intrinsic error resilience of many applications. One of the leading strategies of AxC involves exploring different approximation adder (AxA) configurations as a viable form of reducing power consumption in many applications. This work explores the use of AxAs in a hybrid watermarking technique that combines discrete Haar-Wavelet (DHWT) and discrete cosine transforms (DCT). The proposed hybrid method, HyDHWCT, integrates these transforms to improve robustness and imperceptibility in watermarking systems while optimizing for energy efficiency. We evaluate the performance of various AxAs, including Copy, ETA, LOA, Truncation (Trunc), VLSPPAs, and the AxPPA, regarding energy consumption, circuit area, and error resilience. Our results demonstrate that the AxPPA-based HyDHWCT offers superior accuracy and energy-quality trade-offs over other state-of-the-art AxAs. Specifically, the AxPPA on HyDHWCT with K = 1 achieves up to 72.85% energy savings and 88.32% area savings compared to the exact HyDHWCT while maintaining high accuracy, with a normalized cross-correlation (NC) of 0.9949 and a structural similarity (SSIM) of 0.9920 for the extracted watermark. These results make the AxPPA-based HyDHWCT a highly effective solution for robust and energy-efficient watermarking systems.
This work investigates the use of the Discrete Walsh-Hadamard Transform (DWHT) for cryptographic applications, particularly within resource-constrained environments like microcontrollers such as RISC-V. DWHT's use...
详细信息
ISBN:
(数字)9798331522124
ISBN:
(纸本)9798331522131
This work investigates the use of the Discrete Walsh-Hadamard Transform (DWHT) for cryptographic applications, particularly within resource-constrained environments like microcontrollers such as RISC-V. DWHT's use of adder and subtractor arithmetic operations makes it highly suitable for low-complexity algorithms. In order to enhance efficiency further, our work integrates various approximate adders (AxAs) such as AxPPA, COPY, ETA-I, LOA, and Trunc into both forward (DWHT) and inverse (IDWHT) transform architectures. Our approach outperforms existing methods from the literature regarding accuracy metrics, particularly for lower approximation levels $(K=1\ \text{to}\ K=3)$ , with substantial improvements in PSNR and SSIM. Additionally, our designs significantly reduce power and area compared to existing hardware implementations, show-casing their potential for deployment in real-world cryptographic and hardware security applications.
Multipliers are pivotal in numerous applications, including digital signal processing, image processing, and video processing. Nonetheless, their operation substantially increases power consumption for these applicati...
详细信息
ISBN:
(数字)9798350377200
ISBN:
(纸本)9798350377217
Multipliers are pivotal in numerous applications, including digital signal processing, image processing, and video processing. Nonetheless, their operation substantially increases power consumption for these applications. Therefore, applying strategies that can reduce power in this arithmetic operator is paramount. This paper presents a novel approach to optimize arithmetic units, focusing on multiplier units, through the integration of the Radix- $2^{m}$ squarer unit (RSU) and 4–2 adder/subtractor compressor (AC). Compared to the state-of-the-art, the proposed multiplier unit, termed MRSU (multiplier unit RSU-based), offers significant area-and energy-savings. The synthesis results show remarkable improvements in the MRSU Dadda 4–2 architecture, which achieves 14.35× more energy-savings for 8 bits, 4.87× for 16 bits, and 2.22× for 32 bits compared to the multiplier unit automatically selected by the logic-synthesis tool. Furthermore, compared to the Booth multiplier with the Dadda compression tree, MRSU Dadda 4–2 exhibits 1.67× more energy-savings for 8 bits, 1.93× for 16 bits, and 1.95× for 32 bits.
暂无评论