Open-world Semi-Supervised Learning (OSSL) is a realistic and challenging task, aiming to classify unlabeled samples from both seen and novel classes using partially labeled samples from the seen classes. Previous wor...
Open-world Semi-Supervised Learning (OSSL) is a realistic and challenging task, aiming to classify unlabeled samples from both seen and novel classes using partially labeled samples from the seen classes. Previous works typically explore the relationship of samples as priors on the pre-defined single-granularity labels to help novel class recognition. In fact, classes follow a taxonomy and samples can be classified at multiple levels of granularity, which contains more underlying relationships for supervision. We thus argue that learning with single-granularity labels results in sub-optimal representation learning and inaccurate pseudo labels, especially with unknown classes. In this paper, we take the initiative to explore and propose a uniformed framework, called Taxonomic context prIors Discovering and Aligning (TIDA), which exploits the relationship of samples under various granularity. It allows us to discover multi-granularity semantic concepts as taxonomic context priors (i.e., sub-class, target-class, and super-class), and then collaboratively leverage them to enhance representation learning and improve the quality of pseudo labels. Specifically, TIDA comprises two components: i) A taxonomic context discovery module that constructs a set of hierarchical prototypes in the latent space to discover the underlying taxonomic context priors; ii) A taxonomic context-based prediction alignment module that enforces consistency across hierarchical predictions to build the reliable relationship between classes among various granularity and provide additions supervision. We demonstrate that these two components are mutually beneficial for an effective OSSL framework, which is theoretically explained from the perspective of the EM algorithm. Extensive experiments on seven commonly used datasets show that TIDA can significantly improve the performance and achieve a new state of the art. The source codes are publicly available at https://***/rain305f/TIDA.
This work proposes a hardware architecture for fractional-pixel interpolation filter defined in the royalty-free AV1 video coding standard. Analysis conducted in this work shows that the AV1 Regular family of filters ...
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ISBN:
(数字)9789082797053
ISBN:
(纸本)9781728150017
This work proposes a hardware architecture for fractional-pixel interpolation filter defined in the royalty-free AV1 video coding standard. Analysis conducted in this work shows that the AV1 Regular family of filters has the highest usage especially when considering high resolution videos. The proposed architecture implements the 15 interpolation filters of the AV1 Regular family and is capable to interpolate videos of up to 8K video resolution at 120 fps. The proposed architecture achieves the highest throughput compared to related works.
Adder compressors (AC) have been extensively used in digital circuits like multipliers and transforms where several multi-bit operands have to be summed in parallel. Most available AC structures on the literature do n...
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ISBN:
(数字)9781728134277
ISBN:
(纸本)9781728134284
Adder compressors (AC) have been extensively used in digital circuits like multipliers and transforms where several multi-bit operands have to be summed in parallel. Most available AC structures on the literature do not handle efficiently the intermediary carry propagation on wider bit-widths, potentially leading to longer critical paths and higher energy consumption. Hence, this paper proposes a novel non-hierarchical 8-2 adder compressor CMOS design with limited and constant carry propagation path for N-bit operands, minimizing both circuit delay and power dissipation. The proposed architecture as well as the state-of-the-art ACs are synthesized in a 65 nm CMOS commercial standard cell library, for multiple operands bit-widths. Logic synthesis results show that our proposed design reaches a maximum operating frequency at least 15.2% higher than current state-fo-th-art ACs, while also achieving up to 13.6% of power dissipation savings, increasing the savings with the bitwidth.
This study introduces the Quantum-Train Quantum Fast Weight programmer (QT-QFWP) framework, enabling efficient and scalable programming of variational quantum circuits (VQCs) through quantum-driven parameter updates f...
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ISBN:
(数字)9798331531591
ISBN:
(纸本)9798331531607
This study introduces the Quantum-Train Quantum Fast Weight programmer (QT-QFWP) framework, enabling efficient and scalable programming of variational quantum circuits (VQCs) through quantum-driven parameter updates for the classical slow programmer controlling the fast programmer VQC. By optimizing quantum and classical parameter management, QT-QFWP significantly reduces parameters (by 70–90%) compared to Quantum Long Short-Term Memory (QLSTM) and Quantum Fast Weight programmer (QFWP) while maintaining accuracy. Benchmarking on time-series tasks—including Damped Simple Harmonic Motion (SHM), NARMA5, and Simulated Gravitational Waves (GW)—demonstrates superior efficiency and predictive accuracy. QT-QFWP is particularly advantageous for near-term quantum systems, addressing qubit and gate fidelity constraints, enhancing VQC deployment in time-sensitive applications, and expanding quantum computing’s role in machine learning.
Quantum contextuality, where measurement outcomes depend on the measurement context, implies a failure of classical realism in quantum systems. As recently shown, the transition between measurement contexts can be map...
In this study, the Quantum-Train Quantum Fast Weight programmer (QT-QFWP) framework is proposed, which facilitates the efficient and scalable programming of variational quantum circuits (VQCs) by leveraging quantum-dr...
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The elimination of artifacts is a crucial procedure to extract the full potential of the information into the EEG processing. Embedded systems require low circuit area (cost) and efficient hardware architectures. Adap...
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ISBN:
(数字)9781728160443
ISBN:
(纸本)9781728160450
The elimination of artifacts is a crucial procedure to extract the full potential of the information into the EEG processing. Embedded systems require low circuit area (cost) and efficient hardware architectures. Adaptive filtering plays a vital role as a single method and hybrid approaches for robustly eliminating the noise of the real-world EEG measures. In this paper, we propose and implement hardware architectures for both NLMS and IPNLMS adaptive filters. We investigate the filtering performance and circuit area, timing, and power dissipation of the hardware architecture proposals. To leverage the power-efficiency, we improve our hardware architectures employing the data-gating circuit design technique, which provided up to 20% power savings. Also, applying an HDL-Simulink co-simulation, we perform the hardware architectures tradeoff comparing the synthesis results and filtering performance. Our investigation demonstrates that IPNLMS reduces the time domain error in 11%, increasing less than 1% of circuit area and about the double of the energy per operation, compared to the NLMS.
The rapid advancements in quantum computing (QC) and machine learning (ML) have led to the emergence of quantum machine learning (QML), which integrates the strengths of both fields. Among QML approaches, variational ...
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In this work, we propose a power-efficient hardware architecture for 16-bit m Radix-4 DIT (Decimation in Time) butterfly using radix-2 m multipliers, with m=2, and 4-2 adder compressors. The multiplier uses both Wall...
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ISBN:
(数字)9781728180588
ISBN:
(纸本)9781728180595
In this work, we propose a power-efficient hardware architecture for 16-bit m Radix-4 DIT (Decimation in Time) butterfly using radix-2 m multipliers, with m=2, and 4-2 adder compressors. The multiplier uses both Wallace and Dadda schemes in the addition tree, with Carry-Select, Kogge Stone, and '+' operator from the tool internally. We used a method for a realistic power extraction with the standard delay format. The results show that our best-proposed Radix-4 butterfly saves up to 25% of power dissipation when compared with the original Radix-4 butterfly using the synthesis tool operators for both adders and multipliers. The optimized structure combines the m=2 Wallace-based multiplier, employing Kogge-Stone adder into its addition tree, and 4-2 adder compressors.
This work proposes to optimize iterative-based dividers for a natural logarithm operator design. The logarithm operator approximates the function at the base e. Such an operator is implemented using Taylor Series appr...
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ISBN:
(数字)9781728134277
ISBN:
(纸本)9781728134284
This work proposes to optimize iterative-based dividers for a natural logarithm operator design. The logarithm operator approximates the function at the base e. Such an operator is implemented using Taylor Series approximation. In this approximation, the division is a costly operation. In this work, we explore two iterative-based divider circuits for logarithm operator. We also offer an algorithm responsible for allowing input values different from the ones in the convergence region of the Taylor Series, with a reduced number of iterations. Through co-simulation using both the Matlab ® and ModelSim ® softwares, it was possible to determine the approximation quality of the implemented circuits, with a curve response very close to the Matlab one. Moreover, the Goldschmidt divider presents a slightly fewer relative error, mainly for higher input values comparing with Newton-Raphson. Synthesis results show that although the logarithm circuit with Newton-Raphson divider has marginally more area, it is more power-efficient than the one using Goldschmidt divider.
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